Overview
Best-in-class UART Verification IP for your IP, SoC and system-level design testing.
Best-in-class UART Verification IP for your IP, SoC and system-level design testing. In production since 2014 on dozens of production designs.
Cadence provides a mature and comprehensive Verification IP (VIP) for the UART protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for UART provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for UART helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog along with the Universal Verification Methodology (UVM).
Supported Specification: Standard UART 16550 Specification
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
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Transmission Mode |
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Baud Rate |
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Word Length |
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仿真测试集合
VIP 附带一个场景测试集合,可轻松评估和部署 VIP
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