Overview
I2S Verification IP for your IP, SoC, and system-level design testing.
The Cadence® Verification IP (VIP) for I2S library is a ready-made, highly configurable VIP for the I2S protocol. It allows tests to be run in a pure simulation environment. It provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for I2S is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.
Supported Specification: I2S Specification - Philips Semiconductors.
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
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Configurability |
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Word Length Programmability |
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Default Transactions |
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Functionality |
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仿真测试集合
VIP 附带一个场景测试集合,可轻松评估和部署 VIP
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