Overview
Best-in-class Arm® AMBA® AXI4-Stream Verification IP (VIP) for your IP, SoC, and system-level design testing.
Cadence provides a mature and comprehensive Verification IP (VIP) for the AXI4-Stream specification which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® VIP for AXI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for AXI4-Stream helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Cadence provides a solution for interconnect verification that verifies the correctness and completeness of data as it passes through the SoC. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: AMBA® AXI4-Stream v1.0.
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
---|---|
Data and address widths |
|
UserBusSize |
|
Interface Order Control |
|
Delay control |
|
仿真测试集合
VIP 附带一个场景测试集合,可轻松评估和部署 VIP
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