Overview
Best-in-class Arm® AMBA® LTI Verification IP (VIP) for your IP, SoC, and system-level design testing.
Cadence provides a mature and comprehensive Verification IP (VIP) for the LTI specification, which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence Verification IP for LTI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides Interconnect Validator connection for interconnect verification that verifies the correctness and completeness of data as it passes through the SoC. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for LTI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: AMBA® LTI Protocol Specification (Includes both Issue A and Issue B spec)
Product Highlights
Key Features
The following table shows key features from the specifications implemented in the VIP:
Key Features |
Description |
|---|---|
Supports LTI-A and LTI-B spec version |
|
Channels |
|
Interface management support |
|
Credit Exchange based flow control |
|
仿真测试集合
VIP 附带一个场景测试集合，可轻松评估和部署 VIP
如需更多信息请联系我们
Master Your Tools
Tutorials, Documentation, and Local Experts
Cadence Online Support
Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles