Efficient, Easy-to-Use, and Comprehensive: Revolutionize Your IC Package Design with Allegro X 

Discover the pinnacle of advanced IC packaging design with Allegro X Advanced Package Designer. Empowering designers to navigate the complexities of multi-die packages with unparalleled efficiency, Allegro X Advanced Package Designer offers a platform of powerful features tailored to meet the demands of modern semiconductor packaging. From on-the-fly library development to constraint-driven routing and comprehensive signal integrity analysis, Allegro X ensures first-pass success in designing even the most intricate packages.

Allegro X Advanced Package Designer Platform

Achieve excellence in IC packaging design with a comprehensive, intuitive portfolio

Silicon Layout Option SiP Layout Option Integrity System Planner
Integrity System Planner SiP Layout Option Silicon Layout Option

Design, Characterize, Validate, and Enhance IC Packages with Unwavering Confidence 

Accelerated Package Design

Design intricate multi-die packages with the industry's broadest design rules for advanced substrates, streamlining the process and boosting efficiency by up to 50% with seamless integration and automated layout guidance

Enhanced Design Confidence

Shift left with in-design analysis using Cadence's advanced engines for electrical, EM, and thermal validations, cutting design validation time by over 30% with real-time checks

Facilitates Co-Design and Signoff

Enable seamless co-design between IC packages and digital/analog RFICs with vendor assembly design kits (ADK) for guided layout and signoff, ensuring efficient and reliable multi-die packages while minimizing redesigns and accelerating time-to-market

Empower Your Intricate Designs with Seamless Multi-Die Heterogeneous Integration

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Mastering Modern IC Packaging: From Multi-Die Design to Comprehensive System-Level Management

Powerful Multi-Die Package Implementation

Allegro X Advanced Package Designer allows teams to effortlessly design multi-die packages with on-the-fly library creation, die stacking, embedded cavities, and custom manufacturing outputs using industry-leading design rules.

Optimized Performance and Power Efficiency

With Allegro X Advanced Package Designer, teams can maximize IC package performance, functionality, and power optimization with system-level SiP connectivity modeling and IC I/O pad-ring/array co-design across IC, substrate, and system levels. 

Advanced SiP and Multi-Chip Packaging

Allegro X Advanced Package Designer empowers design teams to capitalize on enhanced SiP design capabilities, seamlessly integrating concept exploration, construction, and validation for high-performance, complex multi-chip packaging technologies 

Comprehensive System-Level Design and Management 

Allegro X Advanced Package Designer encourages teams to benefit from a holistic toolset for seamless system design, including assembly, floorplanning, and connectivity optimization, ensuring optimal performance, cost-effectiveness, and manufacturability.

Next-Gen FOWLP Design 

Adopt cutting-edge fan-out wafer-level packaging (FOWLP) technology with Allegro X Advanced Package Designer Platform. It is tailored for mobile computing, offering thinner profiles, enhanced routing density, and superior heat dissipation for smartphones and tablets. 

Next-Generation IC Packaging Solutions: Bridging the Performance Gap 

Allegro X Advanced Package Designer Silicon Layout Option

Allegro X Advanced Package Designer's Silicon Layout Option is designed to transform FOWLP technology, catering to the demands of the mobile market with its slim designs, enhanced performance, and cost-effectiveness. This innovative tool streamlines the design and verification process, bridging IC backend and package substrate teams.

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  • Optimized for FOWLP Design: Tailored for the specific design and manufacturing challenges of FOWLP, meeting the demands of modern mobile computing.

  • Wafer-Level Implementation: Aligns with IC manufacturing processes, differentiating from traditional organic substrate-based IC package manufacturing.

  • Metal Density Management: Localized metal-density creation and editing tools for ultra-thin packages (500 to 1000µm). Tools for across-design balancing with meshed metal and pads.

  • Advanced GDSII Mask Processing: Enables high-performance mask creation for FOWLP manufacture. 

  • Seamless Integration with Cadence PVS: Direct integration for design and mask verification and signoff to PDK rules deck. PVS verification issue highlighting and reporting directly on design canvas and in constraint manager.

  • Available for Windows (64-bit) and Linux (64-bit).

  • Requires Allegro X Advanced Package Designer and Cadence PVS (sold separately).

Allegro X Advanced Package Designer SiP Layout Option

The Allegro X Advanced Package Designer SiP Layout Option addresses the challenges of system-in-package (SiP) implementation, streamlining the integration of high-pin-count chips onto a single substrate. This technology enables designers to effortlessly explore, capture, and optimize complex multi-chip assemblies and seamlessly integrates with Cadence Innovus technology for chip/package interconnect refinement and Virtuoso technology for RF module design.

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  • Enhanced Multi-Chip Integration: Streamlines integration of high-pin-count chips onto a single substrate for high-performance packaging technologies. 

  • Connectivity-Driven Design: Accelerates planning, optimizing, and timing closure for critical interconnects like DDR memory and high-speed serial interfaces. 

  • Auto-Interactive & Auto-Routing: Provides tools for quick design of complex interconnects, including Specctra-based auto-routing for silicon-based substrates. 

  • Interface-Aware Design: Enables faster routing of standards-based interfaces with hierarchical design capabilities. Simplifies assignment and routing through "flows" representing buses and interfaces. 

  • Full Access to DesignTrue DFM Technology and ARC: Offers comprehensive DesignTrue DFM rules and assembly checks to improve substrate yield and prevent manufacturing issues. 

  • Manufacturability Rules: Defines and applies manufacturability rules in real-time, streamlining the design process with an intuitive spreadsheet interface. 

  • Design and Process Variants: Allows the creation of master designs with multiple configurations, supporting assessment of different stacking and bonding options. 

Integrity System Planner

Integrity System Planner streamlines the entire system design process, from silicon to PCB, by offering assembly, floorplanning, and connectivity optimization. It provides full-system connectivity visualization, allowing instant feedback on system-wide changes and ensuring correct-by-design system assembly. This integrated tool helps achieve optimal performance, cost, and manufacturability, reducing design iterations and cycle times. It is an integral part of the Allegro X Advanced Package Designer Platform and is the cockpit for the Integrity 3D-IC Platform, integrating with Cadence Innovus Implementation System and Cadence Virtuoso Studio.

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  • Streamlined System Design: Manage and assemble the entire design from one source, reducing errors. 

  • Instant Feedback: Visualize full-system connectivity for rapid exploration of design impact. 

  • Optimized Connection: Automatic pin assignment for optimal die-to-die and die-to-substrate routing. 

  • Reduced Iterations: Achieve the right balance for performance and cost before implementation. 

  • Cross-Substrate Solution for Interoperability Across Cadence Products 

  • System-level design connectivity definition and optimization 

  • Management of contact layers between devices 

  • Ability to model complex die stacks with unique design structures 

  • Quickly generate design abstractions for feasibility studies 

  • Drive implementation for all system designs from a common optimized source 

  • Automatic net mapping and propagation across substrates, including differential pairs 

  • Parametric definition and editing of bump and ball pad patterns 

Integrated Solutions for Seamless IC Packaging Implementation

Allegro X Advanced Package Designer Platform enables next generation IC packaging design by integrating unparalleled flexibility, advanced analysis, and packaging optimizations into a seamless workflow. It sets new standards in design efficiency and innovation, supporting cutting-edge technologies to meet modern electronic demands.

Feature name Description
Optimized Physical Layout Solutions Complete solution for single- and multi-die packages with a correct-by-construction database, real-time DRC of physical design rules, and electrical constraints.
Comprehensive Routing Solutions Constraint-driven push-and-shove interactive routing, auto-interactives, and full auto-routing.
Real-Time Design Rule Check Allegro X DesignTrue DFM rule checking integration, with unparalleled flexibility, cutting-edge technology, and comprehensive analysis tools, setting new industry standards for efficiency and innovation.
Advanced Connectivity Model Support Flexible connectivity model, supporting netlist, schematic, and “on-the-fly” connectivity.
Visualize and perform 3D wire and design rule checks Go beyond the constraints of traditional design processes letting you visualize and perform intricate wire and design rule checks in a fully immersive 3D environment.
Advanced Silicon Layout Solutions Localized, tightly controlled metal-density creation and editing tools to control warpage in ultra-thin packages (500 to 1000µm)
Metal-density Utilities  Metal-density utilities for across-design balancing with meshed metal and meshed pads.
High-performance GDSII mask processing Leverage the unmatched capabilities of GDSII mask processing, a critical step in the fabrication of PCB and semiconductor devices.
Seamless and Powerful Integration with Physical Verification System PVS This dynamic synergy offers an unparalleled platform for design verification and signoff directly to the Process Design Kit (PDK) rules deck.
Complete FOWLP Support  Extending the capabilities of IC packaging design tools for both the IC back-end design teams of fabless semiconductor companies and IC package substrate designers, by providing a complete design through verification flow that aligns closely with IC manufacturing processes.
Efficient SiP and Advanced Packaging Development Enabling and integrating design concept exploration, capture, construction, optimization, and validation of complex multi-chip and discrete substrate assemblies.
Interface-Aware Design Apply hierarchical interface-aware approach to accelerate your implementation process in protocols like DDRx, HBM, graphic, and high-speed serial buses —and increase design quality, performance, and reliability along the way.
Early Design Exploration and Tradeoff Analysis This early intervention capability ensures that potential design issues can be identified and addressed long before they become costly problems, saving time and resources.
Shift-Left and Co-Design Optimization Completes I/O pad-ring/array co-design with multi-level optimization across IC, substrate, and system levels. Supports bi-directional ECO and LVS flow for full co-design implementation, alongside feasibility and verification studies for design optimization.
TSMC’s Integrated Fan-Out (InFO) Packaging Technology Support Integrated design flow using Cadence IC-level and package design tools to provide a seamless flow with enhanced features for InFO technology, reducing overall design turnaround time.
Cell-level Power Integrity Supports comprehensive electromigration and IR-drop (EM-IR) design rules and requirements while providing full-chip system-on-chip (SoC) power signoff accuracy.

Your Next System Design in Allegro X Advanced Package Designer Platform 

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Start your next IC Packaging Design with Allegro X Advanced Package Designer Platform