News Release
Overview
Reduce Risk and Improve Productivity
In a business environment, where design timelines are shrinking, while the need for custom solutions increases, design teams are relying more than ever on reputable, reliable IP solutions. With this increasing complexity, connectivity fabric complexity also increases. Cadence Janus NoC System IP, a highly configurable, high-performance, network-on-chip IP, addresses this complexity, from the subsystem level all the way up to multi-chiplet systems.
Key Benefits
Higher Productivity with Reduced Risk
Intuitive Design Entry Tool
Use a powerful GUI to generate a NoC configuration, then submit the configuration to get RTL and SystemC models
Highly Configurable
Configure BW, latency, clock domain crossings, clock gating, buffer size, and pipeline stages—everything you need to achieve your target PPA goals
Scalability
Start with subsystem design, then take the same design and create a full SoC; Need a higher level of integration? No problem, we can do chiplets as well
Cadence Is Your Trusted Partner
With a vast IP portfolio, full suite of development tools, and unmatched support
Features
Simple and Efficient Interconnect for the Most Complex SoC Designs
What's New
培训 & 支持
