System Design and Verification, Digital Physical Design and Signoff Onboarding Training
版本 | 区域 | |
---|---|---|
1.0 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 4.4 Days (35 hours)
Course Description
Accelerate your onboarding in System Design and Verification, as well as Digital Physical Design and Signoff, by taking a curated series of our online courses and passing the badge exams for each class.
- First, we provide a high-level overview of semiconductors and the EDA industry with the Semiconductor 101 course.
- Then, learn about the fundamentals of the digital design flow with the Digital IC Design Fundamentals course.
- Next, you will learn the complete RTL2GDS flow using Cadence tools with the Cadence RTL-to-GDSII Flow course.
Learning Objectives
After completing the courses, you will learn about:
- Moore's law and its impact on the chip's performance, manufacturing process, and costs
- How chip design is different from other types of design
- Systems, stacked dies, and how emulation and prototyping are used before fabrication
- Semiconductor markets
- Cadence Intelligent Design Strategy
- The design flow with Cadence EDA tools
- How the industry transitioned from fabs to fabless companies
After completing the courses, you will be able to:
- Draw a flow diagram of the entire design flow and explore the entire ASIC design flow process
- Identify the distinction between Digital IC design, verification, and implementation
- Recognize the different stages of front-end design and verification
- Demonstrate the SystemVerilog HDL for design and verification
- Recognize the different stages of design implementation
- Create, verify, and implement a system-level design with a simple architecture
- Identify the challenges of scaling, costs, and physical attributes, as well as low power and area constraints before tapeout
- Identify the different processes in the semiconductor industry used to handle the above realistic challenges
- Code a design in Verilog to the design specification that is provided
- Compile, elaborate and simulate your design
- Synthesize your design
- Design for test
- Run equivalency checking at different stages of the flow
- Floorplan a small design
- Run placement, optimization, clock tree synthesis, and routing on your design
- Run signoff checks to make sure that the design chip can be fabricated
- Write out a GDSII
Software Used in This Course
Please refer to the individual course datasheets for software and versions.
Software Release(s)
Each course URL contains the software release information for that course.
Modules in this Course
Audience
- Electronics or Computer Engineering Graduates
- CAD Engineers
- Place and Route Engineers
- Design Engineers
- ASIC Designers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- Programming
- Electronics or Computer Engineering
Related Courses
Course ID: 86366
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