UCIe VIP Introduction Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
11.30.094 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 3 Days (24 hours)
Become Cadence Certified
Course Description
This course is an introduction to UCIe VIP. This is a VIP model for UCIe protocol, which can be used to test UCIe DUT. It generates UCIe traffic and collects data to verify the functionality of DUT. It also provides the coverage model to track verification progress. This is implemented as independent UCIe layers and can be instantiated as a single layer or all three layers together.
Learning Objectives
After completing this course, you will be able to:
- Explain the high-level architecture of all the Cadence® VIP
- Integrate UCIe VIP in your verification environment
- Configure UCIe VIP as per your requirements
- Set up and run a simulation with UCIe VIP Full Stack example
- Write additional testcases in the verification environment of the Full Stack example
- Utilize callbacks for
- Analyzing transaction flow
- Packet modification
- Error insertion
- Analyze and Debug simulation output using log files
- Debug verification environment using transaction Waveform Debugger in the Verisium™ Debug tool
- Analyze coverage goals using the IMC Cadence tool
Software Used in This Course
- VIPCAT
- XCELIUM
- VERISIUMDEBUG
Software Release(s)
VIPCAT113;XCELIUM2309;VERISIUMDEBUG2309
Modules in this Course
- Architecture
- Integration
- Configuration
- VIP Layer Description
- Test Writing
- Callbacks
- Messaging and Debug
- Coverage
- Error Injection
Audience
- Existing UCIe VIP customer
- Verification Engineer willing to use UCIe VIP
- Verification Engineer willing to explore Cadence VIP
Prerequisites
You must have experience with or knowledge of the following:
- Have knowledge of verification using SV-UVM
- Have experience with simulation environments and execution
- Have a basic understanding of UCIe protocol
- Have access to the simulation tool (for labs)
Related Courses
- SystemVerilog for Design and Verification
- Essential SystemVerilog for UVM Training
- SystemVerilog Accelerated Verification with UVM Training
- Xcelium Simulator Training
- Verisium Debug Training
Course ID: 86338
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