Mixed Signal Verification with UVM Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
23.09 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 1.5 Days (12 hours)
Become Cadence Certified
Course Description
In this course, you learn Mixed-Signal verification with UVM. The Accellera standard Universal Verification Methodology - Mixed Signal (UVM-MS) architecture is used to develop a mixed-signal testbench and verify the Mixed-Signal Design Under Test (MS-DUT). You get to analyze different components inside the UVM-MS testbench and different aspects of analog mixed-signal communication.
For this course, you use the command-line-based Xcelium™ Use model that uses the xrun executable to run the simulations.
You are also introduced to the Cadence® Mixed-Signal IP and SOC Verification Solution and Mixed-Signal Metric Driven(MS-MDV) methodology.
Learning Objectives
After completing this course, you will be able to:
- Set up and run UVM-MS testbench to verify mixed-signal design
- Analyze the different verification components (UVCs), and AMS and DMS communication
- Use the randomization approach for
precise verification of analog blocks
- Perform assertion-based checks on analog
signals
- Perform SPICE metric driven block level verification with the
Verisium™ Manager
Software Used in This Course
XA310 Xcelium Digital Mixed Signal
App
70060 Spectre
AMS Connector
90006 Spectre/Multi Mode
Tokens
X300 Xcelium Single
Core
29010 SimVision Mixed-Signal
Debug Option
VERMGR Verisium Manager
Software Release(s)
Xcelium 23.09-s003, Spectre 23.1 (ISR3)
Modules in this Course
- Introduction to UVM-MS
- UVM-MS Components
- Analog Resource
Communication
- UVM-MS
Additional Features
- Adapting MDV to Mixed-Signal
Designs
- Appendices: UVM Basics
and SystemVerilog Real Number Modeling
Examples
Audience
- Analog/Mixed-Signal IC Designers
- Analog/Mixed-Signal Verification Engineers
- Digital Verification Engineers
Prerequisites
Before taking this course, you need to have:
- A good working knowledge of SystemVerilog and UVM
Or you must have completed the following courses:
- SystemVerilog Accelerated Verification with UVM
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Behavioral Modeling with Verilog-AMS
- Real Modeling with SystemVerilog
Related Courses
The following are related courses to Mixed-Signal Verification.
- Mixed Signal Simulations Using Spectre AMS Designer
- SimVision for Debugging Mixed-Signal Simulations
- Real Modeling with Verilog-AMS
- Analog Modeling with Verilog-A
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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