Genus Synthesis Solution with Stylus Common UI Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
23.1 | Online | ENROLL |
22.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 3 Days (24 hours)
Become Cadence Certified
Course Description
In this course, you learn about the features of the Cadence® Genus™ Synthesis Solution with Stylus Common UI with next-generation synthesis capabilities (massively parallel, tight correlation, RTL design focus and Architecture-level PPA) and how SoC design productivity gap is filled by Genus. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, run physical synthesis, optimize for low-power structures, analyze DFT (design for testability) constraints, and interface with other tools in the Genus Stylus CUI. You will be able to identify the steps required to perform logic optimization for digital design and generate various input and output files.
You also learn how to run a complete synthesis flow on a design with the given specifications and optimize it for area, timing, and power using the Stylus Common UI. You will learn to query the design database and set attributes for synthesis flow in the Genus Stylus CUI. You explore Multi-Mode Multi-Corner (MMMC) Synthesis Flow in Genus. You also identify Flowkit and Unified Metrics capabilities.
Learning Objectives
After completing this course, you will be able to:
- Identify the features of Genus™ and Stylus Common User Interface
- Apply the recommended synthesis flow using the Cadence® Genus Synthesis Solution
- Explain multi-mode multi-corner (MMMC)
- Debug design scenarios
- Describe the extended datapath features
- Optimize designs using the physical synthesis flow
- Analyze and synthesize the design for low-power structures
- Constrain the design for testability (DFT)
- Identify the interface to the Conformal® equivalence checker and other tools
- Describe Flowkit and Unified Metrics
- Explain Unified Safety Format
Software Used in This Course
- Genus Synthesis Solution
Software Release(s)
Genus 23.1
Modules in this Course
- Overview of Genus Synthesis Solution Stylus Common UI
- Getting Started with Genus Synthesis Solution
- Working in Genus Shell
- Synthesis Flow in Genus
- Finding Information in the Genus Design Hierarchy
- Exploring Genus Synthesis Solution Stylus Common UI GUI (Optional)
- Editing the Netlist
- Reducing Runtime
- Debugging Design Scenarios
- Datapath Synthesis
- Genus Physical Synthesis
- Low-Power Optimization
- Test Synthesis
- Interfacing with LEC and Other Tools
- Flowkit and Unified Metrics (Optional)
- Unified Safety Format
Audience
- ASIC Designers
- Digital IC Designers
- Logic Designers
Prerequisites
You must have experience with or knowledge of the following:
- Any HDL such as Verilog (recommended) or VHDL
- Synthesis and ASIC design flow basics
- Static Timing Analysis
Or you must have completed the following courses:
Related Courses
- Genus Synthesis Solution
- Logic Equivalence Checking with Conformal EC
- Innovus Digital Implementation (Block)
- Innovus Digital Implementation (Hierarchical)
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus
"It is an excellent course. The new environment is amazing."
Nikos Georgoulopoulos, Aristotle University of Thessaloniki
“Having two competent trainers who took their turns in presenting the separate sessions worked nicely."-Blended Course-
Alexander Hradetzky, Infineon
“Course content and instructor explanation on each module was very good.”-Blended Course-
Kavitha Shekarappa, Infineon