Real Number Modeling with SystemVerilog Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
23.03 | Online | ENROLL |
19.09 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 3 Days (24 hours)
Become Cadence Certified
Course Description
In this course, you focus on Real-Number Modeling (RNM) using the SystemVerilog language in a mixed approach, borrowing concepts from the digital and analog domains to enable high-performance, digital-centric, mixed-signal verification.
In the course, you learn how to model analog block operation as discrete real data to improve top-level verification performance using SV real data type and nettypes. It stresses SystemVerilog 2012 Extended Nettype Capabilities (built-in, UDT/UDR) and Interconnects. You learn to use the Cadence® package "EE_pkg" that defines nettype "EEnet" to describe analog impedance-based interactions between blocks in a SystemVerilog DMS environment. You then examine advanced RNM features, SV port connections, and Connect Modules (CM) for AMS interactions. The nettype debug and performance improvement are discussed. Most of the labs in this course are in command-line mode using the Xcelium™ simulator with the mixed-signal option. In addition to that, you work with SystemVerilog Models and Packages in the Virtuoso® environment.
Learning Objectives
After completing this course, you will be able to
- Identify how Real-Number Modeling (RNM) using SystemVerilog enables high-performance digital-centric, mixed-signal SoC verification
- Create real-number models with SystemVerilog real variables and nettypes
- Apply the real modeling techniques for creating analog operations and functions
- Identify SystemVerilog 2012 Extended Nettype Capabilities (built-in, UDT/UDR) and Interconnects
- Examine the Cadence package “EE_pkg” that defines nettype “EEnet" for electrical pin modeling
- Explore advanced SVRNM features and Connect Modules (CM) for AMS interactions
- Identify how SV port connections are resolved in mixed designs using wildcard (.*) notation
- Debug the Nettype (UDT/UDR) struct values using Tcl commands and system functions
- Improve performance with incremental elaboration at the SVRNM partition boundary
Software Used in This Course
- Xcelium Digital Mixed-Signal App
- Xcelium Single Core
- Xcelium Limited Single Core
- SimVision Waveform Display
- Spectre AMS Designer
- Spectre AMS Connector
- Spectre Multi-Mode Simulation with AMS
- Virtuoso Schematic Editor
- Virtuoso Simulation Environment
- Virtuoso ADE Explorer and Assembler
- Virtuoso Visualization & Analysis
Software Release(s)
XCELIUM 23.03 (23.03-s005), SPECTRE 23.1.0.63, IC 6.1.8-64b.500.33
Modules in this Course
- Introduction to Real Modeling
- SVRNM Basics
- SV Real Modeling Techniques
- Advanced SVRNM Modeling Techniques
- Modeling Electrical Circuits Using Cadence "EE_pkg"
- SVRNM Capabilities and Interactions
- SVRNM Debug and Performance Improvement
- Optional Appendices
- SV-RNM in the Virtuoso Environment
- SystemVerilog Basics
- SV Real Number Modeling Examples
Audience
- Verification engineers, verification leads, designers, and managers interested in improving the predictability, productivity, and quality of mixed-signal SoC verification runs
- Analog and mixed-signal SoC verification engineers looking to learn about event-based behavioral modeling techniques
- Digital and SoC verification engineers looking to achieve >100X to 500X performance improvements in their nightly regression runs
Prerequisites
You must have a working knowledge of Verilog and SystemVerilog languages and experience working with the AMS Designer simulator, and have completed the following courses:
- SystemVerilog for Design and Verification
- Mixed-Signal Simulations Using Spectre AMS Designer
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
Related Courses
- SystemVerilog for Design and Verification
- Mixed-Signal Simulations Using Spectre AMS Designer
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Real Modeling with Verilog-AMS
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
Free Online Training Bytes (Videos)ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus
"The course was of high quality. I liked that it presented numerous examples and comparisons between VerilogAMS and SystemVerilog. The instructor met every expectation;(...) he explained well for both engineers with digital as well as those with analog background."
Mihai-Liviu Ursescu, Infineon Technologies
"I'm happy with the training. The trainer is a real pro. The matters discussed, although very difficult, were clearly explained!”-Blended Course-
Maciej Kachel, IPHC - University of Strasbourg
“I very much liked the course: it was well organized and detailed. I liked very much the examples provided during the lecture. The instructor was always ready to answer questions, discuss related topics and support during lab exercises.”
Giuseppe Bernacchia, Infineon Technologies
"The course material is very well done and rich with instrumental details."
Marco Carlini, STMicroelectronics
"The adequate guidance and expertise by the trainers allowed me to master the hands-on sessions, therefore enhancing the overall learning experience.”-Blended Course-
Lee Roy Theodore, Infineon Technologies
"Slides are made very good.”-Blended Course-
Davide DeBelli, Infineon Technologies