SystemC Language Fundamentals Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
12.2 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 3 days (24 Hours)
Become Cadence Certified
Course Description
This course teaches the IEEE Standard 1666-2011 SystemC® Language. You perform the lab exercises using the Incisive® Enterprise Simulator XL.
Learning Objectives
After completing this course you will be able to:
- Identify where SystemC fits in your design flow
- Construct and simulate a SystemC modules
- Model design data using SystemC data types
- Model design behavior using SystemC processes
- Define, implement, and utilize SystemC interfaces
- Trace the scheduling of simulation events
- Construct and use primitive channels
- Construct and refine hierarchical channels
- Query simulation runtime information
- Report and diagnose incorrect design operation
Software Used in This Course
- Incisive Enterprise Simulator XL
Software Release(s)
INCISIV122
Modules in this Course
- SystemC applications
- SystemC language introduction
- SystemC data types
- Processes and events
- Interfaces and channels
- SystemC simulation engine
- Building channels
- Simulation query and control
- Debugging SystemC
Audience
- Design Engineers
- System Engineers
- Verification Engineers
Prerequisites
You must have experience with or knowledge of the following:
- Knowledge of hardware or software design or verification
- Practical working knowledge of C and C++
- Basic UNIX literacy. You must know how to use a shell and editor of your choice and navigate the file system.
Related Courses
- Incisive SystemC, VHDL, and Verilog Simulation
- C++ Language Fundamentals for Design and Verification
- SystemC Transaction-Level Modeling (TLM 2.0)
Click here to view course learning maps, and here for complete course catalogs.
Course ID: 82202
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus