Cadence Showcases PCIe 7.0-Ready IP at PCI-SIG Developers Conference 2023
PCIe 7.0 continues to progress through draft stage, IP enablement begins
Overview
Cadence® PHY IP for PCI Express® (PCIe®) 7.0 is a high-performance NRZ/PAM4 SerDes multi-protocol PHY that is PPA optimized for high-performance computing (HPC) and artificial intelligence and machine learning (AI/ML) applications. The ultra-long-reach equalization, robust clock-data recovery capabilities, low data path latency and low power consumption make it ideal for deployment in time-sensitive applications in HPC, AI/ML, data communications, networking, and storage systems. This multi-protocol PHY is highly versatile and scalable and can be configured to support X1, X2, X4, X8, and X16 lane widths with embedded bifurcation capability that allows multiple PCIe links of various link widths to co-exist and operate independently in the same macro.
Key Benefits
High Performance
DSP-based equalization and clock-data-recovery (CDR) offer unmatched channel loss handling performance and reliability
Flexibility
Highly configurable PHY with support for PCIe, CXL, and common electrical standards
Lowest Risk
Brings Cadence’s expertise in PAM4 and PCIe together in the implementation of this emerging standard
Ease of use
Fully verified, pre-integrated IP delivery with package and signal integrity support and firmware for faster bring-up