Analog-Mixed Signal Design Modeling Onboarding Training
日期 | 版本 | 国家/地区 | 位置 | |
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Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
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1.0 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 10 Days (80 hours)
Course Description
Capturing the design intent through structural and behavioral language-based modeling of analog/mixed signals is an integral part of many design flows.
Whether you are a block-level designer or a mixed-signal verification engineer, this onboarding course on analog/mixed-signal modeling is curated for engineers exploring these facets using Cadence® tools and methodologies.
You can benefit from a structured curriculum that starts with creating models using the Verilog-A/Verilog-AMS languages within the Virtuoso® Design Environment. You can use either the Spectre® AMS Designer simulator or the Xcelium™ Mixed-Signal Simulator environment to verify the functionality of your designs.
The latter two courses in this curriculum are focused on using real-number modeling (RNM) concepts that enable you to perform digital-centric mixed-signal verification.
Here are some examples that will give you a glimpse of what to expect from this course:
- What are Disciplines and Natures in Verilog-A and Verilog-AMS
- Defining a Verilog-AMS Model
- Analog and Real Modeling,What is the DIfference?
- WREAL Implementation of A/D and D/A Converters
The above links take you to training video snippets on the Cadence® Learning and Support page. You will need an authenticated account to log in and view these videos.
This course consists of multiple classes. After completing each class, you can attempt a quiz to achieve a digital badge.
Learning Objectives
After completing this course, you will be able to:
- Determine the importance of the top-down methodology for accelerating complex system development
- Create Verilog, Verilog-A and Verilog-AMS behavioral models to express functionality
- Verify the functionality and performance of the models that you create using the Spectre AMS Designer Simulator
- Generate a library of common functions for smoothing discontinuous behavior and model common analog effects
- Create and verify the functionality and performance of Verilog-AMS wreal models using the Spectre AMS Designer simulator
- Resolve wreal connectiions in mixed-signal designs
- Review tips and tricks that you can apply while creating and simulating wreal models
- Identify how Real-Number Modeling (RNM) using SystemVerilog (SV) enables high-performance digital-centric, mixed-signal SoC verification
- Create RNMs with SV real variables and nettypes
- Explore SV-RNM features and Connect Modules (CM) for mixed-signal interactions
- ....and many more
Software Used in This Course
- Xcelium Digital Mixed-Signal App
- Xcelium Single Core
- Spectre AMS Designer
- Spectre AMS Connector
- SimVision™ Waveform Display
- Spectre Circuit Simulator
- Virtuoso Schematic Editor
- Virtuoso ADE Explorer
- Virtuoso ADE Assembler
- Virtuoso Visualization and Analysis
Software Release(s)
IC231, SPECTRE231, XCELIUM243, IC618
Modules in this Course
This course consists of multiple classes. After completing each class, you can attempt a quiz to achieve a digital badge. It is advisable to take these classes sequentially.- Analog Modeling with Verilog-A
- Behaviroal Modeling with Verilog-AMS
- Real Number Modeling with Verilog-AMS
- Real Number Modeling with SystemVerilog
Audience
- Analog/Mixed-Signal Designers
- Analog/Mixed-Signal Verification Engineers
- Modeling and Digital/Mixed-Signal Verification Engineers
Prerequisites
You must have experience with or knowledge of the following
- Coding concepts
- Unix commands
- The Virtuoso Design Environment
- Mixed-Signal concepts
Also, it's suggested that you complete the following courses for a better understanding of the material covered in this course. The Virtuoso ADE courses will help with easier navigation through the environment
- SystemVerilog for Design and Verification
- Mixed-Signal Simulations Using Spectre AMS Designer
- Command-Line Based Mixed-Signal SImulations with the Xcelium Use Model
- Verilog Language and Application.
Related Courses
- SystemVerilog for Design and Verification
- Mixed-Signal Simulations Using Spectre AMS Designer
- Command-Line Based Mixed-Signal SImulations with the Xcelium Use Model
- SimVision for Debugging Mixed-Signal Simulations
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus