Virtuoso Spectre Transient Noise Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
IC23.1&SPECTRE23.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 Days (16 hours)
Become Cadence Certified
Course Description
In this course, you learn to perform Transient Noise Analysis using the Spectre® Simulator in the Virtuoso® Analog Design Environment (ADE) Suite. After a brief introduction to the Spectre Transient analysis, you learn the different types of Spectre Noise Analyses. This is followed by in-depth coverage of the Spectre Transient Noise Analysis, along with the various parameters and options used while carrying out this analysis. Then, a discussion is carried out on the Power Spectral Density (PSD) using different methods. Further, you learn to perform a variety of Transient Noise-related Simulations and compare the results with Small-Signal AC Noise, Periodic Noise (pnoise), and Harmonic Balance Noise (hbnoise). Further, you learn the Jitter calculations using the Transient Noise Analysis using different Virtuoso Visualization and Analysis XL Calculator functions and compare the results with those from different functions in the sampled Periodic Noise (pnoise) Analysis. Finally, you learn to use the Multiple Runs option in the Transient Noise Simulations and compare the results with small signal AC Noise.
Learning Objectives
After completing this course, you will be able to:
- Define the Transient Noise Analysis
- Set up and run the Transient Noise Simulations
- Observe the effect of parameters like Noise Seed, Power Spectral Density, Noise Fmax, Noise Fmin, and noisescale on the Transient Noise results
- Compare the results of Transient Noise Simulations with AC Noise (noise), timeaverage Periodic Noise (pnoise) and timeaverage Harmonic Balance Noise (hbnoise)
- Define Jitter and perform different types of Jitter Measurements Using Transient Noise and sampled Periodic Noise (pnoise) Analyses
- Perform the Simulations with Multiple Runs option in Transient Noise Analysis
Software Used in This Course
- Virtuoso ADE Explorer
- Virtuoso ADE Assembler
- Virtuoso Schematic Editor L
- Spectre Classic Simulator
- Spectre RF option for 38500 and 91050
- Spectre X Simulator
Software Release(s)
IC 23.1 (ISR2) and SPECTRE 23.1 (ISR1)
Modules in this Course
- Introduction to Transient Noise Analysis
- Transient Noise Simulations
- Jitter Analysis
- Using the Multiple Runs Option in Transient Noise Analysis
Audience
- Analog IC Designers
- Analog/Mixed-Signal IC Designers
- Chip Designers
- Custom Circuit Designers
- RF Designers
Prerequisites
Before taking this course, you need to
- Have an understanding of analog circuit design and theory
- Have the ability to read and understand analog (SPICE) circuit netlists
- Have a basic knowledge of the Virtuoso Schematic Editor and Virtuoso ADE Explorer/Assembler
- Have used the Spectre Circuit Simulator from the Virtuoso environment
- Have an understanding of Transient Analysis
- Have an understanding of different types of Noise Analyses in the Spectre platform
Or you must have completed the following courses:
- Virtuoso Schematic Editor
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Spectre Simulator Fundamentals S1: Spectre Basics
- High-Performance Spectre Simulation
- Spectre RF Analysis Using Harmonic Balance
- Spectre RF Analysis Using Shooting Newton Method
Related Courses
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre RF Analysis Using Harmonic Balance
- Spectre RF Analysis Using Shooting Newton Method
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus