Cadence Cerebrus Intelligent Chip Explorer Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
23.1 | Online | ENROLL |
22.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 1 Day (8 hours)
Become Cadence Certified
Course Description
The Cadence® Cerebrus™ Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus will intelligently optimize the Cadence digital full flow to meet these power, performance, and area (PPA) goals in a completely automated way. By adopting Cadence Cerebrus, it is possible for engineers to concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. Additionally, through the Cadence Cerebrus full-flow reinforcement learning technology, engineering team productivity is greatly improved.
Learning Objectives
After completing this course, you will be able to:
- Identify the features of Cadence Cerebrus Intelligent Chip Explorer
- Set up implementation flow optimization
- Define and adjust primitives to improve cost functions like power, performance, and area
- Create a base flow and run multiple scenarios
- Analyze the results from a basic Cadence Cerebrus run
- Debug failed scenarios
- Compare design metrics from various design phases
Software Used in This Course
- Cadence Cerebrus Run Manager
- Cadence Cerebrus Genus™ Option
- Cadence Cerebrus Innovus™ Option
- Cadence Cerebrus Tempus™ Option
Software Release(s)
CEREBRUS231 DDI231
Modules in this Course
- Introduction to Machine Learning
- Building Blocks of Cadence Cerebrus
- Running Cadence Cerebrus
- Debugging and Analyzing Your Cadence Cerebrus
- Cadence Cerebrus Apps
Audience
- ASIC Designers
- Flow Developers
Prerequisites
You must have experience with or knowledge of the following:
- Innovus, Genus, and Tempus
Related Courses
Innovus Block Implementation with Stylus Common UI
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus
“it’s a very good course for the basic of Cerebrus (…) it has explained everything very perfectly”-Online Course-
Amit Saha, Synapse Design