Jasper Design Bringup Training
版本 | 区域 | |
---|---|---|
2303 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 3 hours
Course Description
This course is intended for RTL designers who have basic knowledge of SystemVerilog Assertions (SVA). This course illustrates how to use Jasper™ static analysis and Formal Property Verification as "instant testbench" generators, enabling efficient testing and hunting of bugs as part of an RTL development process. This can result in orders-of-magnitude productivity gain for a project, accelerating discovery and correction of many issues that would otherwise need to be found and debugged in a larger validation environment.
Learning Objectives
After completing this course, you will be able to:
- Describe and execute the methodology for the initial bring-up of RTL designs using Jasper
- Develop an effective RTL design exercise plan
- Demonstrate features of Jasper that can help with RTL structural and behavioral exploration
- Demonstrate the types of static analysis that can be performed, including clock and reset analysis
- Effectively evaluate an RTL design to obtain confidence that the expected good behaviors can be demonstrated
- Explore design behaviors and write properties that can be used by other team members and by simulation
- Identify incorrect behaviors through the process of exploring expected behaviors
Software Used in This Course
Jasper Formal Apps
Software Release(s)
Jasper 2303
Modules in this Course
Setup and Installation of an Example Design
- Review Jasper setup concepts
- Overview of example design
- Black Boxing
- Compiling the RTL
Basic Static Analysis in Jasper
- Viewing model hierarchy
- Using the Design Browser
- Using the Clock Viewer
- Reset Analysis
- Querying Design Info
Exercising the Design using Jasper FPV
- Creating an Exercise Plan
- Proving Cover Properties as an "Instant Testbench"
- Analyzing & Interacting with Waveforms in Visualize
- Modifying Properties and Generating New Waveforms
- Re-generating Waveforms with New Assumptions
Audience
Design and Verification Engineers involved in RTL development
Prerequisites
- You must have one month of experience writing properties with SVA
- You must be familiar with Formal Property Verification
Or you must have completed the following courses:
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