Pegasus Verification System Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
23.1 | Online | ENROLL |
22.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 Days (16 hours)
Become Cadence Certified
Course Description
The Cadence® Pegasus™ Verification System is a cloud-ready physical verification signoff solution that enables engineers to deliver Advanced Node Integrated Circuits (ICs) to market faster. The groundbreaking technology delivers up to 10X improved performance on DRC runs and reduces turnaround time from days to hours. The Pegasus system's innovative architecture and TrueCloud processing provide an elastic and flexible computing environment. The Pegasus system provides a massively parallel architecture, delivering near-linear scalability across 100s of CPUs. The Pegasus system's Giga scale technology enables full-chip signoff DRC in just a few hours versus days.
Virtuoso®iPegasus™offers a comprehensive Pegasus-based, in-design, integrated, andinteractive sign-off quality DRC and Fill on your designs, using thefoundry-qualified rule decks to reduce overallturnaround time.
The Pegasus
system integrates with the industry-standard Cadence
Virtuoso custom/analog platform, the market-leading
Cadence Innovus™ Implementation System,
Allegro®, and mixed-signal flows.
This course has been designed for user-level physical design verification. You run DRC, LVS, ERC, PERC, FastXOR, and iPegasus checks to find and debug layout errors in your design. You set up options, run verification, and use Pegasus Results Viewer to locate, analyze, and fix the violations. Under LVS checks, you debug shorts and stamping conflicts using features like Interactive Shorts Locator (ISL), Probing form, and Stamping Conflict Debugger. Use FastXOR to compare a stream file with an existing OpenAccess cell view.
In this course, the Virtuoso Layout Suite is used for layout design access, where the Pegasus Verification System comes integrated.
You can visit the Cadence
and Learning Support Landing Page: Pegasus™
Verification System to learn more about
Pegasus.
Learning Objectives
After completing this course, you will be able to:
Identify the features and Advance Debug solutions in Pegasus Set up and run Pegasus DRC, ERC, LVS, PERC, and FastXOR in GUI and batch modes Debug DRC, ERC, LVS, PERC, and FastXOR violations in the Pegasus Results Viewer Explore the Pegasus Configurator feature Check the Pegasus Design Review (PDR) platform Define and debug stamping conflicts Debug LVS shorts with the Pegasus Interactive Short Locator (ISL) Interactively verify and fill with the Virtuoso Studio iPegasusCreate and manage snapshots for the Virtuoso Studio iPegasus
Review Pegasus tips and reference info on the Cadence Learning and Support
Software Used in This Course
- Virtuoso Studio
- Pegasus Verification System
Software Release(s)
PEGASUS 23.1, IC 23.1
Modules in this Course
Running FastXOR (Optional) Extended Practice for DRC and LVS (Optional)
Audience
- Physical layout designers who need to verify layout designs
Prerequisites
You must have:
- Knowledge and experience with physical design and verification
- Familiarity with the Virtuoso Layout Suite
Related Courses
- SystemVerilog for Design and Verification
- Virtuoso Schematic Editor
- Virtuoso Layout Design Basics
- Virtuoso Connectivity-Driven Layout Transition
- Physical Verification System
- Physical Verification Language Rules Writer
- Assura Verification
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus
Transistor-Level T3: Extracted View Flows and
Advanced Features
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