Tensilica Xtensa NX Processor Interfaces Training
版本 | 区域 | |
---|---|---|
8.4 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 1 day (8 Hours)
Course Description
This one hour course provides information about Tensilica® NX processor technology and how to use Tensilica product deliverables for your SoC design. You explore topics regarding the Xtensa® NX processor interfaces. This includes the following interfaces:
- Clocks, resets and control
- Local memory interfaces and caches
- Processor bus interfaces
- TIE interfaces
- Debug and trace interfaces
The solid fundamentals taught in this course enable you to quickly become productive in the use of Xtensa processors for your SoC design.
Learning Objectives
After completing this course, you will be able to:
- Understand Xtensa NX interfaces in depth
- Understand the use case examples of each interface
- Design your SoC with the best use of Xtensa NX interfces
Software Used in This Course
- Tensilica SW Release RH-2018.7
Software Release(s)
RH-2018.7, RI-2018.0
Modules in this Course
- Clocks, Resets and Control
- Caches and Local Memory
- Processor Bus Interfaces
- TIE Interfaces
- Debug and Trace Interfaces
Audience
- SoC architects designing systems with Xtensa processors
- Architects/Designers configuring Xtensa processors for a specific application
- Design verification engineers
Prerequisites
You must have experience with or knowledge of the following:
- Basic microprocessor architecture
- RTL design for hardware engineers
And you must have completed the following courses:
- Tensilica Xtensa NX Processor Fundamentals
Related Courses
- Tensilica Xtensa NX Hardware Verification & EDA
- Tensilica Instruction Extension Language and Design
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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