Xcelium Integrated Coverage Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
24.03 | Online | ENROLL |
20.09 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 Days (16 hours)
Become Cadence Certified
Course Description
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course explores Xcelium™ Integrated Coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of VHDL, Verilog and mixed-language designs. Not all coverage features are available with all languages. The course uses the Integrated Metrics Center for reporting and analysis and then discusses the collection and analysis of the following types of coverage:
- Code (branch, expression, toggle, state, and arc) coverage
- Data-oriented functional coverage using SystemVerilog covergroups
- Control-oriented functional coverage using SystemVerilog assertions and the PSL
Learning Objectives
After completing this course, you will be able to:
- Effectively use the Xcelium integrated coverage with your VHDL, SystemVerilog, and mixed-language designs
Software Used in This Course
- Xcelium Single Core
- Verisium™ Manager Linux Client
Software Release(s)
XCELIUM2403, VersiumMANAGER2403
Modules in this Course
- Introduction to Xcelium Integrated Coverage
- Identifying Coverage Types
- Identifying Code Coverage
- Defining Data Coverage with SystemVerilog Covergroups
- Defining Control Coverage with SystemVerilog Assertions
- Defining Control Coverage with PSL
- Generating Coverage Data
- Textually Analyzing Coverage Data
- Graphically Analyzing Coverage Data
Audience
- Verification Engineers
Prerequisites
You must have:
- Familiarity with the VHDL or SystemVerilog languages, and with design and design verification.
- Familiarity with SystemVerilog covergroups, and SystemVerilog and PSL assertions. This course reviews them only briefly.
Related Courses
- VHDL Language and Application
- Verilog Language and Application
- SystemVerilog for Design and Verification
- The Xcelium Simulator
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus
"My experience with your on line trainings is very positive, especially because it is possible to balance the working activity and the training time, and (...) to repeat parts where important concepts are given.”
Stefano Serafini, Sciosense