Fundamentals of IEEE 1801 Low-Power Specification Format Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
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11.0 | Online | ENROLL |
10.0 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
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Length: 1 Day (8 hours)
Course Description
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This one-day course is a complete tutorial for understanding the fundamentals of IEEE 1801 low-power specification format concepts. You learn about IEEE 1801 power supply networks, ground ports and nets, creating and connecting supply ports/nets, power domain, power switch, power states, defining isolation and level shifter strategies, hierarchical IEEE 1801, and various versions of the IEEE 1801. You also explore how power intent information can be used for a design across various stages of flow, such as functional verification, synthesis, logic equivalency checking, place-and-route, test, timing signoff, power integrity, and so forth using Cadence® tools.
Learning Objectives
After completing this course, you will learn:
- Review concepts of low power
- Identify the evolution of IEEE 1801
- Identify IEEE 1801 concepts
- Identify the Power Supply Network (PSN), power state, power domain interface
- Write IEEE 1801 for MSV/PSO design
- Identify retention, isolation, and level shifter strategy
- Implement a power switch
- Identify low-power strategies with IEEE 1801
- Identify the concept of hierarchical IEEE 1801
- Review the three versions of IEEE 1801
- Debug design scenarios
- Analyze non-standard IEEE 1801 coding styles
- Describe Cadence tools supporting IEEE 1801
- Set up and run IEEE 1801 flow for Cadence tools
Software Used in This Course
- Conformal Low Power Verify
Software Release(s)
CONFRML 241
Modules in this Course
- Low-Power Concepts
- IEEE 1801 Introduction
- IEEE 1801 Basic Concepts
- Examples of IEEE 1801 Format for MSV/PSO Design
- Low-Power Strategies
- Hierarchical IEEE 1801
- Reviewing the Three Versions of IEEE 1801
- Debugging Design Scenarios
- Non-Standard IEEE 1801 Coding
- Cadence Tools Flow and Setup for IEEE 1801
Audience
- Verification Engineers
- Place and Route Designers
- IC Designers
- Hardware Engineers
- Electrical Engineers
- ASIC Designers
- Design Engineers
- Circuit Designers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- HDL
- Logic design
- Basics of ASIC design
Related Courses
- Low-Power Flow with Innovus Implementation System
- Low-Power Synthesis Flow with Genus Stylus Common UI
- Conformal Low-Power Verification with CPF
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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