Tensilica Instruction Extension Language and Design Training
版本 | 区域 | |
---|---|---|
9.3 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 1 day (8 Hours)
Course Description
This one-day training class introduces Tensilica® Instruction Extensions (TIE) and teaches the basics of writing TIE. You will be introduced to some of the most useful TIE constructs, their syntax, and examples of how to use them. You will learn how to create processor extensions that improve the processing performance as well as data bandwidth for your application code. Five labs covering different topics will provide hands-on experience in writing TIE code. This class is highly recommended for designers writing TIE or for those interested in learning about the TIE processor extension methodology.
Learning Objectives
After completing this course, you will be able to:
- Create TIE instruction extensions for an Xtensa® processor core
- Use TIE instructions in your application software to improve performance
- Ensure efficient hardware implementation of your TIE instructions
Software Used in This Course
- Xtensa Software Tools Release RI-2020.6
Software Release(s)
RI-2020.6
Modules in this Course
TIE Introduction
- Overview of TIE
- Typical Instruction Extensions
Creating a TIE Operation and Using in Software
- TIE Development Flow
- TIE Operation: Creating a new Instruction
- TIE intrinsic: Using Instruction in C/C++ Code
- Lab 1: Endian Conversion
- TIE Verification
- TIE state
- TIE regfile
- Using Data-Level Parallelism
Improving Out-of-box Software Performance
- Datatypes and Prototypes
- Aides for Context Switching and Debugging
- Lab 2: SIMD
- FLIX
- Lab 3: FLIX
Scheduling and Sharing Datapaths
- Scheduling TIE Operations
- Merging Computation of Multiple TIE Operations
Creating Modular TIE
- Built-in Modules
- User-defined Modules
- Multi-cycle Modules
- Lab 4: Hardware Sharing using TIE Semantic
- Xtensa NX Pipeline Overview
- Inter-Pipeline Data Movement in TIE Operations
- Defining Load/Store Operations for Xtensa LX
- Defining Load/Store Operations for Xtensa NX
- TIE Ports in Xtensa LX and Xtensa NX
- TIE Queue Interfaces in Xtensa LX
- TIE Queue Interfaces in Xtensa NX
- TIE Lookup Interfaces in Xtensa LX and Xtensa NX
Audience
- Architects/Designers creating TIE extensions to an Xtensa processor for a specific application
- Other software/hardware engineers working extensively with Xtensa processors
Prerequisites
You must have experience with or knowledge of the following:
- Basic microprocessor architecture
- Programming in C/C++ for software engineers
- RTL design for hardware engineers
Related Courses
- Tensilica LX Processor Fundamentals
- Tensilica NX Processor Fundamentals
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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