Virtuoso Layout for Advanced Nodes Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
ICADV12.2 | Online | ENROLL |
IC23.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 Days (16 hours)
Become Cadence Certified
Course Description
The increased demand for fast and efficient semiconductor chips that are smaller in size and consume less power is constantly growing. One way to achieve this is by reducing the chip geometry. However, using advanced process nodes to achieve these goals can pose various design challenges. These challenges include complex layout rules, increased power and timing variability, and the need to handle large designs with a significant amount of intellectual property (IP).
Advanced chip technology beyond 20 nm requires double patterning. Traditional routing architectures are struggling with complex and dense chips. Small errors cause significant problems. Silicon failures, performance degradation, and prolonged schedules create a predictability crisis. High-k metal gate, SOI, and 3-D packaging add pressure to adopt advanced technologies quickly.
This course takes designers through the back-end tools required to do 20 nm and below physical design, including a review of the 20 nm process and technology requirements, Multiple Patterning (MPT), wiring setup, variations of editing path segments using Create Wire, and Create Bus, streaming in/out Precolored data, device placement constraints with respect to dummy devices, diffusion rules, Track Patterns, and Constraint Overrides. iPegasus DRC and Fill for the Virtuoso® Studio.
Learning Objectives
After completing this course, you will be able to:
- Understand and meet the requirements for setting up and creating physical designs using IC 23.1 software at 20nm and below
Software Used in This Course
- IC 23.1
Software Release(s)
IC 23.1
Modules in this Course
- Advanced Node Technology Overview
- FinFET Grids, Snap Patterns, Placement, and Abutment
- EXL Layout Generation
- MPT Introduction
- Color Verification
- Advanced Node Constraints
- Width Space Patterns (WSP)
- iPegasus DRC and Fill for the Virtuoso Studio
Audience
- Physical Designers
- Layout Engineers
Prerequisites
You must have experience with or knowledge of the following:
- Virtuoso Layout Suites XL and EXL
Or you must have completed the following courses:
Related Courses
- Virtuoso Layout Design Basics
- Virtuoso Layout for Advanced Nodes: T1 Place and Route
- Virtuoso Layout for Advanced Nodes: T2 Electromigration
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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