Real Number Modeling with Verilog-AMS Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
22.03 | Online | ENROLL |
14.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 Days (16 hours)
Become Cadence Certified
Course Description
In this course, you learn how Real Number Modeling using Verilog-AMS (wreal) enables high-performance digital-centric, mixed-signal verification. You must have a working knowledge of the Spectre® AMS Designer simulator, or you must take the Mixed Signal Simulations Using Spectre AMS Designer course.
In this course, you learn how to model analog block operation as discrete real data for high-performance digital-centric, mixed-signal SoC verification. You explore the advanced capabilities of wreal by examining how wreal connections are resolved in mixed designs.
You create Verilog-AMS wreal models and verify their functionality and performance using the Spectre AMS Designer or Xcelium™ Simulator with Mixed-Signal Option in both the command line and the Virtuoso® design environment.
Learning Objectives
After completing this course, you will be able to:
- Identify how Real Number Modeling using Verilog-AMS (wreal) enables high-performance digital-centric, mixed-signal verification
- Create Verilog-AMS wreal models
- Verify the functionality and performance of the wreal models that you create using the Spectre AMS Designer simulator
- Use the advanced wreal modeling features
- Identify how wreal connections are resolved in mixed designs
- Apply the wreal modeling techniques for creating models
- Review some of the tips and tricks that you can apply while creating and simulating wreal models
Software Used in This Course
- Spectre AMS Designer
- Spectre AMS Connector
- Xcelium Single Core
- Xcelium Digital Mixed-Signal Option (Xcelium Digital Mixed-Signal App)
- Virtuoso ADE Explorer
- Virtuoso Schematic Editor
- Virtuoso Visualization and Analysis XL
- SimVision Waveform Display
Software Release(s)
Xcelium 22.03-s005, Spectre 21.1(ISR11) , IC6.1.8(ISR26)
Modules in this Course
- Introduction to Real Modeling
- wreal Model Creation and Simulation
- wreal Modeling Techniques
- Special Features of wreal
- Debugging Tips and Tricks
- Optional Appendixes
- Mixed-Signal Licensing and xrun Options
- wreal Modeling Constructs and Guidelines
- Waveform Viewers
Audience
- Analog/Mixed-Signal IC Designers
- Analog/Mixed-Signal IC Verification Engineers
- Digital Modeling and Verification Engineers
Prerequisites
You must have completed the following courses:
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Mixed Signal Simulations Using Spectre AMS Designer
- Behavioral Modeling with Verilog-AMS
- Verilog Language and Application
Related Courses
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Mixed Signal Simulations Using Spectre AMS Designer
- Behavioral Modeling with Verilog-AMS
- Verilog Language and Application
- Analog Modeling with Verilog-A
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus
“Excellent training.”
Vladimir Majkic, NXP Semiconductors
“Instructor is excellent. Explanations are very detailed!”-Online Course
Goran Georgijev, Veriest
“Content was specifically tuned to what we need – very good!”
Sven de Knibber, Melexis
"Very valuable course with a good blend of lecture and lab exercises. Good style of lab exercises: first time to solve alone, then together on screen. Good structure: starting with Verilog, then VerilogA and finally combining both."
Josef Zipper, NXP Semiconductors
“I like the clear and understandable form of course material. The lecturer was able to answer all additional questions during the course.”
Andrey Kazarinov, Melexis