Physical Verification System Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
23.1 | Online | ENROLL |
22.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 Days (16 hours)
Become Cadence Certified
Course Description
Click here for a Course Preview.For faster and better performance in advanced node complex designs verification, Cadence® recommends our latest tool, Pegasus Verification System, instead of PVS.
In the Physical Verification System (PVS) course, designed for user-level physical design verification, you run DRC, LVS, ERC, PERC, FastXOR, and Constraint Validation checks to find and debug errors in your design. You set up the options, run DRC, and use PVS DRC Results Viewer or DRC Debug Environment to locate and fix design rule violations. Similarly, you will set up, run, and debug ERC violations, including stamping conflicts. After the LVS run, you will use the Interactive Shorts Locator (ISL) feature in the LVS debug environment to locate and correct the shorts. You will set up constraints using the Virtuoso® Constraint Manager and validate them with the PVS Constraint Validator. You then set up and run VIPVS (Virtuoso Integrated PVS) in Post-Edit and Verify-Design modes for in-design DRC checking. Finally, you will invoke PVS FastXOR to compare a stream file with an existing OA cell view.
The PVS verification features are integrated into the Virtuoso Studio Layout Suite menus for easy access.
Learning Objectives
After completing this course, you will be able to:
- Check where PVS fits in the Cadence SSV Solution
- Overview of the features and capabilities of PVS
- Explore the Advanced Debug solutions in PVS
- Set up and run PVS DRC in GUI and batch modes
- Debug violations with the PVS Results Viewer, DRC DE, and Annotation Browser
- Explore the PVS Configurator feature
- Examine the PVS DRC Waivers flow
- Explore the PVS Design Review platform
- Set up and run PVS ERC in GUI and batch modes
- Define and debug Stamping Conflicts
- Set up and run PVS PERC in GUI and batch modes
- Explore topology checks from PVS PERC
- Set up and run PVS LVS in GUI and batch modes
- Clean shorts with the Interactive Shorts Locator
- Troubleshoot LVS violations with the Graphical LVS Debugger
- Set up and run VIPVS in Post-Edit and Verify Design modes
- Create and manage snapshots for VIPVS
- Run VIPVS in Dynamic Rules Filtering mode
- Understand the concept of Constraint Validation in PVS
- Invoke, set up, and run PVS CV in the Virtuoso platform
- Debug Constraint Violations with PVS RV and Annotation Browser
- Run PVS CV and debug violations in the Virtuoso Constraint Manager
- Explore the various types of constraints supported by PVS CV
- Set up and run PVS FastXOR in GUI and batch modes
- Review PVS tips
Software Used in This Course
- Virtuoso Studio Layout Suite IC23.1
- Virtuoso Layout Suite IC618
- Physical Verification System
Software Release(s)
PVS 23.1, IC 23.1, IC 6.1.8
Modules in this Course
- PVS Introduction
- Design Rule Checking
- Electrical Rules Checking
- Programmable ERC (Optional)
- Layout Versus Schematic
- Virtuoso Interactive PVS
- Constraint Validation in PVS
- Running FastXOR (Optional)
- Extended Practice for DRC and LVS (Optional)
Audience
- Physical layout designers who need to verify layout designs
Prerequisites
You must have:
- Knowledge and experience with physical design and verification
- Familiarity with the Virtuoso Layout Suite
Related Courses
- Pegasus Verification System
- Physical Verification Language Rules Writer
- Virtuoso Schematic Editor
- Virtuoso Layout Design Basics
- Assura Physical Verification
- Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
- Virtuoso Connectivity-Driven Layout Transition
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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