Allegro FPGA System Planner Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
16.6QIR6 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 days (16 Hours)
Course Description
In the Allegro® FPGA System Planner (FSP) course, you learn to define your FPGA system and synthesize the connections in your design. You generate a schematic and PCB Editor database, so the FPGA I/O assignments can be optimized in the board environment.
This course requires the SPB16.6 QIR6 (HotFix 27) software or later.
Learning Objectives
After completing this course, you will be able to:
- Identify how data flows from the FPGA System Planner (FSP) to the schematic and PCB
- Create a design in FSP
- Define the protocols and interfaces in an FSP design
- Synthesize the connections in FSP protocols and interfaces
- Add terminations and external ports in an FSP design
- Generate an Allegro Design Entry HDL schematic from your FSP design
- Export your FSP placement to the PCB Editor
- Backannotate pin swaps and design changes from the schematic and PCB Editor to FSP
Software Used in This Course
- Allegro FPGA System Planner
- Allegro Design Entry HDL
- Allegro PCB Editor
Software Release(s)
- SPB 16.6QIR6 (HotFix 27)
Course Agenda
Day 1
- FPGA System Creation
- FPGA System Synthesis
- FPGA System Completion
Day 2
- Integration with Design Entry HDL and PCB Editor
- Postlayout Optimization
- Importing FPGA Constraint Files and Virtual Interfaces
- FSP Models
Audience
- Design Engineers
- FPGA Designers
- PCB Designers
Prerequisites
You need to have experience with or already have knowledge of Logic Design.
Related Courses
Click here to view course learning maps, and here for complete course catalogs.
Course ID: 84479
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