Behavioral Modeling with Verilog-AMS Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
24.03 | Online | ENROLL |
20.09 | Online | ENROLL |
14.2 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 Days (16 hours)
Become Cadence Certified
Course Description
In this two-day course, you can explore an in-depth approach to behavioral modeling of analog and mixed-signal design blocks and systems. Firstly, you examine digital modeling concepts and later analog and mixed-signal modeling concepts. You can create parameterized Verilog-AMS models for analog and mixed-signal blocks and verify their functionality and performance using the Spectre® AMS Designer Simulator in the Virtuoso® environment or the Xcelium™ Mixed-Signal Simulator environment.
As optional modules, you can identify how to handle analog interdependencies, modeling in the frequency domain, and the Waveform Specification (wave) feature in the ADE Assembler environment for validating models, along with basic information on the Waveform Viewers like the Virtuoso Visualization and Analysis and SimVision graph windows to examine the mixed-signal simulation results.
Learning Objectives
After completing this course, you will be able to:
- Apply the concepts of behavioral modeling and know when to employ models to your advantage
- Create Verilog, Verilog-A, and Verilog-AMS behavioral models to perform the given functions
- Verify the functionality and performance of the models that you create using the Spectre AMS Designer Simulator
- Generate a library of common functions for smoothing discontinuous behavior and model common analog effects
- Explore some of the best practices for modeling analog components
- Interpolate with table models and explore the different system tasks and functions in Verilog-AMS
Software Used in This Course
- Spectre AMS Designer
- Spectre Simulators (MMSIM)
- Xcelium Single Core
- Xcelium Mixed-Signal App
- Virtuoso ADE Explorer
- Virtuoso ADE Assembler
- Virtuoso Visualization and Analysis XL
- SimVision™ Waveform Display
This course uses Xcelium 24.03 with IC 23.1 ISR7 and SPECTRE 23.1 (ISR8) software.
The lab exercises cover both the command-line control-based model with the XRUN executable (AXUM) and the Virtuoso-based flow (AVUM), which uses Text Editors for coding and performs simulation using Spectre AMSD in the ADE Explorer.
Software Release(s)
XCELIUM 24.03-s003, IC 23.1(ISR7), SPECTRE23.1(ISR8)
Modules in this Course
- Getting Started with AMS Modeling
- Refresher in Behavioral Verilog
- Verilog-AMS Language Constructs and Simulation
- Continuity Issues in Analog Modeling
- Modeling Common Analog Effects
- Best Practices for Analog Modeling
- Verilog-AMS Mixed-Signal Operation
- Simulator Functions in Verilog-AMS
- General Modeling Procedures
(Optional Appendixes)
- Analog Interdependencies
- Modeling in the Frequency Domain
- Waveform Specification in the ADE Assembler
- AMSD Licensing and xrun Options
- Waveform Viewers
- Verilog-A Usage and Language Summary
- Verilog-HDL Usage and Language Summary
Audience
- Analog/Mixed-Signal IC Designers
- Analog/Mixed-Signal Verification Engineers
- CAD Engineers
- Library Developers
Prerequisites
You must have experience with the following software:
- AMS Designer Simulator
- Virtuoso ADE Explorer
Or you must have completed the following courses:
- Analog Modeling With Verilog-A
- Mixed Signal Simulations Using Spectre AMS Designer
- Command-Line Based Mixed-Signal Simulations With The Xcelium Use Model
Related Courses
- Real Modeling with Verilog-AMS
- SimVision for Debugging Mixed-Signal Simulations
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Analog Modeling with Verilog-A
- Mixed-Signal Simulations Using Spectre AMS Designer
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus
"Perfect."
Marian Poncik, ON Semiconductor
“Thank you very much for allowing engineers to improve their knowledge and skills. (...) instructors are very good, dedicated areas are covered and explanations are detailed." -Online Course-
Goran Georgijev, Veriest
"Good overview course. Labs are very effectively supporting the learning progress.”
Andreas Weitzer, NXP Semiconductors
"Interesting and useful training with strong relation to my current job."
Jan Chromcak, ON Semiconductor
"Very valuable course with a good blend of lecture and lab exercises. Good style of lab exercises: first time to solve alone, then together on screen. Good structure: starting with Verilog, then VerilogA and finally combining both."
Josef Zipper, NXP Semiconductors
“Content was specifically tuned to what we need – very good!”
Sven de Knibber, Melexis
"The training was well prepared and very informative."
Martin Kejhar, ON Semiconductor
“I like the clear and understandable form of course material. The lecturer was able to answer all additional questions during the course.”
Andrey Kazarinov, Melexis
"Thanks a lot for this(…)course! Great lecturer. It is very clear and interesting(...). The pace is high but comfortable. Course content is well structured, easy to navigate."-Online Course-
Andrii Buzuluk, Melexis