Verilog Language and Application Training
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
28.0 | Online | ENROLL |
27.0 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 4 Days (32 hours)
Course Description
The Verilog Language and Application course offers a comprehensive exploration of the Verilog HDL and its application to ASIC and programmable logic design. The course provides a solid background in the use and application of the Verilog HDL to digital hardware design. This training course covers all aspects of the language, from basic concepts and syntax through synthesis coding styles and guidelines to advanced language constructs and design verification. It also touches upon ASIC library design concepts.
Learning Objectives
After completing this course, you will be able to:
- Use fundamental Verilog constructs to create simple designs
- Ensure that Verilog designs meet the requirements for synthesis
- Develop Verilog test environments of significant capability and complexity
Software Used in This Course
- Xcelium
- Genus Synthesis Solution
Software Release(s)
XCELIUM23.09, GENUS21.1
Modules in this Course
- Describing Verilog Applications
- Verilog Introduction
- Choosing Between Verilog Data types
- Using Verilog Operators
- Making Procedural Statements
- Using Blocking and Nonblocking Assignments
- Using Continuous and Procedural Statements
- Understanding the Simulation Cycle
- Using Functions and Tasks
- Directing the Compiler
- Introducing the Process of Synthesis
- Coding RTL for Synthesis
- Designing Finite State Machines
- Avoiding Simulation Mismatches
- Managing the RTL Coding Process
- Managing the Logic Synthesis Process
- Coding and Synthesizing an Example Verilog Design
- Using Verification Constructs
- Coding Design Behavioral Algorithmically
- Using System Tasks and System Functions
- Generating Test Stimulus
- Developing a Testbench
- Example Verilog Testbench
Audience
- Design Engineer
- Verification Engineer
Prerequisites
You must have knowledge of the following:
- How to navigate a file system and use a text editor
- A basic understanding of digital hardware design and verification.
Related Courses
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Free Online Training Bytes (Videos)ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus
“Excellent training with high quality trainer”-Blended Course-
Fabrice Voisin, IN2P3
"I learned a lot during the Verilog language course. Thanks to the very professional lecturer who makes sure that everyone understands everything. (...). I recommend this course for those who want to study Verilog from the beginning."
Stas Litski, Intel
“This course was very interesting and I really appreciated the teacher's explanations.”-Blended Course-
Ludovic Alvado, IN2P3
"Well structured training! Balance between lab exercises and theoretical lessons very well met! Increased my insight on digital development a lot!”
Erich Loew, NXP Semiconductors
"I believe that I learned enough to read the code of an existing implementation to understand what it is performing."
Manel Rodriguez Millan, Applus
“Principal Verilog instructor. He could answer every question.”
Eirini Psyrra, NXP Semiconductors
“Very good impression. The trainer has a lot to share with the trainee, on top of the shared slides, with concrete examples, so that this is a rich & fruitful training”-Blended Course-
David Gaillard, STMicorelectronics