Chip-Package Co-Design on High-Performance Transceivers Using Virtuoso RF Solutions
In this paper we present how ADI has successfully employed Cadence’s Virtuoso-RF flow for chip-package co-design and demonstrate how it offers significant advantages over existing approaches. Currently, chip-package co-design is supported with a two-tool methodology where Virtuoso is employed for chip design and schematic entry, and where Allegro is employed for package design. As ADI’s single-IC-in-package and SiP products increase in complexity, and as time-to-market continues to be a key business objective, the bridge between Virtuoso and Allegro is becoming a critical bottleneck. In this new methodology package design can now be done directly inside Virtuoso through a multi-technology framework. Some of the many features of this new methodology include: IC layouts and packages and can be directly overlaid on each other within the Virtuoso environment, package layouts are easily transportable between Virtuoso and Allegro, and chip-package layouts can be probed all from within Virtuoso. The new methodology brings a host of advantages to ADI’s design process. Planning of bump and ball layouts can now be done far more efficiently. Critical package nets can be designed and optimized within Virtuoso with IC layouts present, and then easily moved to Allegro. Debug and probing of package designs is now as convenient as what is found in existing chip-design flows. Co-design becomes a more practical reality. Using ADI’s RF transceiver products, we will illustrate some of the many advantages offered by this new methodology for large SoC package developments.
Watch VideoCo-Modeling of IC+Package Using EMX Software
It is well known that accurate modeling of interconnect lines and other passive components - example spiral inductors - is essential for correctly predicting the performance of IC designs. Tools such as QRC (and its predecessors) have been successfully used for over two decades to rapidly extract accurate distributed RC models of large IC layouts. As circuit speeds increased, broadband models became a necessity for critical signal nets, which in turn drove the need for fast and accurate IC-level electromagnetic solvers. Tools such as EMX, specifically designed for this purpose, have been successfully used for modeling both interconnect and passive structures up to 80 GHz and beyond. For example, at Analog Devices EMX is an essential tool in the design of nearly all our transceiver and RF products – to name just two product areas. As IC performance and speed both continued to increase, package performance and speed followed, and hence tools and flows were developed to support the electromagnetic modeling of complex package designs. This in turn has led to a new modeling challenge that is now upon us: the co-modeling of IC + package, where electromagnetic coupling between IC and package, and signal chain behavior from circuit through to package ports, can significantly impact system performance. Failure to co-model these physically distinct domains can be very costly, and in the worst can force a re-spin of not just a package design but of one or more ICs. Electromagnetic simulation tools traditionally used for package modeling can be coaxed to include IC-level interconnect and passive structures in a simulation. But this approach can run into challenges when dealing with the many complexities of deep submicron back end of line technologies. Alternatively, tools targeted for IC-level modeling, that have been designed for submicron technologies, can usually be more easily coaxed to include key package elements. In this talk we will focus on the latter approach. We will present examples from our RF and transceiver product lines where we have successfully used EMX to simulate IC + package. We will also review the key assumptions that are in play when extending EMX to IC + package and the accuracy limitations that arise. In addition, we will address the topic of ground planes in the context of an IC + package simulation, and the importance of understanding the fundamental differences between ideal and physical grounds. We will conclude with a summary and an outline of plans for future work.
Watch VideoDesigning 5G/mmW Products in the Cadence Cloud on AWS
Interest in 5G and millimeter wave (mmW) devices is rapidly expanding in today’s world. From 5G small cells and phased arrays, to automotive radar, to IoT devices, the challenges of accurately designing and modeling these projects requires a stable platform and dedicated hardware resources that run efficiently, especially for a company that has limited resources to devote to maintaining that environment. As a startup based in Moorestown, NJ, Otava utilizes the Cadence cloud that is hosted through the Amazon Web Services (AWS) to enable our product development. Designing for 5G and mmW products requires the use of several tools seamlessly, and 3rd party tools are able to be loaded into the cloud environment to support the team’s design. The cloud approach to hardware and software maintenance allows designers to focus on what they do best – design. Otava’s mmW flow through AWS effectively delivered a complex ultra-wideband mmW beamforming SoC within a year with only six designers scattered across multiple states, with the design coming back demonstrating first pass millimeter wave performance.
Watch VideoFrom Radar to Radios: System and Microwave Design
From radar to radio systems design, Cadence AWR software platform enables RF/microwave engineers to move from concepts to prototypes. This presentation will touch upon basic radio system design through construction and demonstration of a quadrature amplitude modulated (QAM) radio. Fundamentals of signal processing, pulse shaping for reduce bandwidth, noise and maximum capacity of a system will be covered as well. Lastly, the microwave components such as couplers, power dividers and phase shifters using transmission lines as well as active devices such as mixers, low noise amplifiers (LNAs) will be discussed.
Watch VideoLoop Gain Envelope Amplifier Stability Analysis Using Microwave Office
Will discuss the loop gain envelope stability analysis theory and show how to use the technique in Microwave Office focusing on a practical PA design example. Was requested by Microwave Office team to present.
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