Overview
JESD204 Verification IP for your IP, SoC, and system-level design testing.
Cadence provides a mature and comprehensive Verification IP (VIP) for the JESD204 protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for JESD204 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for JESD204 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM).
Supported Specification: JESD204B and JESD204C
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
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Topology |
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Clock Frequency |
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Initial Lane Alignment |
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Encoding Type |
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Simulation Test Suite
VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.
Please contact us for further information.
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