Overview
Best-in-class PIPE PHY Verification IP for your IP, SoC and, system-level design testing.
The Cadence PIPE PHY Verification IP (VIP) provides a mature, highly capable verification solution for the PHY layer of complex protocols such as PCIe 3/4/5/6, USB3.x, USB4, DisplayPort and SATA at the Intel PIPE (PHY Interface for PCI Express*, SATA, USB3, DisplayPort, and Converged IO Architectures). The VIP supports the simulation platform and enables metric-driven verification of IP and system-on-chip (SoC) designs against PIPE PHY protocol specifications. PIPE PHY VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators.
Supported Specifications: Intel PIPE version 4.3, 4.4,1, 5.x and 6.x specifications.
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
---|---|
Device Type |
|
PHY Architecture |
|
Pin Interface |
|
Protocols Mode |
|
Simulation Test Suite
Extensive testsuite, coverage model, and verification plan with clear linkage to the specification for simple and fast compliance testing.
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Cadence Online Support
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