Overview
Best in class MIPI® UniPro Verification IP for your IP, SoC, and system-level design testing.
In production since 2011 on dozens of production designs.
Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the MIPI ® UniProsm Protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for UniPro helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported Specifications: MIPI UniPro v1.6, v1.8 and v2.0 and M-PHY v4.0, v4.1, and v5.0.
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
---|---|
Serial and RMMI Interfaces |
|
CPort Signal Interface |
|
All Layers Supported |
|
Built-In Sequences |
|
Data Link Layer |
|
Simulation Test Suite
Extensive testsuite, coverage model, and verification plan with clear linkage to the specification for simple and fast compliance testing.
Master Your Tools
Tutorials, Documentation, and Local Experts
Cadence Online Support
Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles