Overview
The gold standard JEDEC DDR5 DIMM memory device for your IP, SoC, and system-level design verification.
First to market with full DDR5 DIMM support.
This Cadence Verification IP (VIP) provides support for the JEDEC DDR5 SDRAM Unbuffered, Registered, and Load-Reduced DIMM Design Specification, the DDR5 UDIMM/RDIMM/LRDIMM standard. It provides a mature, highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model VIP for DDR5 DIMM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
Product Highlights
Key Features
The following table describes key features from the specification that are implemented in the VIP:
Feature Name |
Description |
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DIMM Types |
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Size |
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Speed |
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DRAMs |
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