Overview

Best-in-class CXL Verification IP for your IP, SoC, and system-level design testing.

The Cadence Verification IP (VIP) for Compute Express Link (CXL) is part of the Cadence family of VIP for PCI Express® (PCIe®). Built on top of Cadence's mature industry-leading VIP for PCIe, the CXL VIP provides a complete bus functional model for all three CXL protocols, CXL.io/CXL.mem/CXL.cache, and allows users to verify both CXL host, device and Switch designs for all device types (Type 1, 2, 3) from the very first days of the CXL protocol.

CXL diagram

Product Highlights

  • Supports CXL3, CXL2, CXL1.1
  • Built on top of proven PCIe Gen6 VIP
  • Supports all 3 semantics (.io, .cache, .mem)
  • Supports device types, such as CXL Host, Device, Switch, or PHY designs
  • Supports Serial(NRZ, PAM4) and PIPE 6.2 (Original, Serdes Architecture) specification
  • Dynamic activation support to enable the user to set the VIP as active or passive without changing the testbench while determining the instance to instantiate during run time
  • Extensive functional coverage model, verifical plan, and testsuite available

Key Features

The following table describes key features from the specifications that are implemented in the VIP.

Feature Name

Description

Device Configuration
  • Host, Device, Switch

Spec Version
  • 3.0, 2.0, 1.1

Device Type
  • Type 1: Caching Devices/Accelerators: CXL.io, CXL.cache
  • Type 2: Accelerators with Memory: CXL.io, CXL.cache, CXL.mem
  • Type 3: Memory Buffers: CXL.io, CXL.mem

Protocol Support
  • CXL.io, CXL.mem, CXL.cache

Interface
  • Serial (NRZ, PAM4) and PIPE 6.2

Link Rate
  • Native support of 64GT/s, 32 GT/s, and downgraded support of 16GT/s and 8GT/s

Link Width
  • Native widths (x16, x8, x4) and degraded widths (x2, x1)

Flit Support
  • CXL 3 256B Flit, 128B L0pt (Latency Optimized)
  • CXL2 64B Flit

Register Space
  • Configuration space registers (CXL DVSEC)
  • Memory-mapped registers
  • CXL RCRB support for 1.1 backward compatibility testing

Flex Bus Support
  • Alternative Protocol Negotiation
  • Framing and packet layout
  • Framing error handling
  • Physical Layer Latency Optimization (Sync Header Bypass, Drift Buffer)
  • Replay mechanism for CXL3

Enumeration
  • Bypass enumeration
  • Auto-enumeration for CXL DVSEC and Memory Mapped register space

Arb/MUX
  • vLSM/ALMP Low Power
  • Deepest Allowable Power Management (DAPM)
  • Weighted round-robin
  • Arbitration bypass mode
  • ALMP/vLSM bypass

Enumeration
  • CXL 1.1 and 2.0 enumeration
  • Bypass enumeration
  • Auto-enumeration for CXL DVSEC and Memory Mapped register space
CXL.io
  • Fully backward compatibility to PCIe 6.0, PCIe 5.0
  • Memory type indication on ATS
  • PM VDM
  • Deferrable Memory Write (DMWr)

CXL.mem
  • M2S Req/RwD
  • S2M NDR/DRS
  • M2S Req/S2M NDR, DRS (Type 2 flow)
  • Forward progressing rules
  • Speculative memory read
  • Memory error reporting
  • QoS telemetry

CXL.cache
  • D2H request/response
  • H2D request/response
  • Back-Invalidation Snoops (CXL3.0 feature)
  • Host, Device Bias modes
  • Cache and Snoop filter modeling

Mem/Cache Link Layer
  • CXL3, CXL2 Flit Slots support
  • Flow Control for CacheMem
  • Retry flow (RRSM, LRSM) for CXL 2.0
  • ACK/LLCRD forcing
  • Viral and Poison support

Integrity and Data Encryption (IDE)
  • Supported for CXL3.0, CXL2.0
  • CXL.io/CXL.mem/CXL.cache encryption
  • Authentication: DOE/SPDM/CMA for Discovery, Negotiation, Device attestation, Key negotiation, Bypass mode,
  • Operational modes: Containment and Skid
  • Error handling
CXL 3.0
  • Cache Back-Invalidation
  • Retry flows
  • Enhanced Low Power
  • L0p
  • Throttle
  • NOP Hint
CXL Switch
  • .mem packet routing supported via Hierarchy Based Routing (HBR)
  • .mem packet routing supported via Port Based Routing (PBR)
  • .cache packet routing supported via CacheId
  • .io packet packet routing supported as per PCIe mechanisms
Multi-Logical Support
  • LD-ID support for .io and .mem packets
CXL 3.0 ECN
  • Extended Meta-data
System Plugins
  • System-level scoreboard
  • System Performance Analyzer

Simulation Test Suite

Extensive testsuite, coverage model, and verification plan with clear linkage to the specification for simple and fast compliance testing.

TripleCheck Test Suite

Master your tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

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CadenceTECHTALK

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