Overview
Cadence's best-in-class Verification IP (VIP) for MIPI® CSI-2sm for IP, SoCs and, system-level design testing.
In production since 2008 on dozens of production designs.
Cadence provides a mature and comprehensive VIP for the CSI-2 protocol, which is part of the MIPI family. Incorporating the latest protocol updates, the Cadence® VIP for CSI-2 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CSI-2 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: MIPI CSI2 v1.3, v2.0, v2.1, v3.0, v4.0, MIPI D-PHY v1.2, v2.1, v2.5, MIPI C-PHY v1.0, v1.2, v2.0, MIPI CSE v1.0, MIPI PAL/CSI2 v1.0, and MIPI A-PHY v1.0.
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
---|---|
PHY Interfaces |
|
PPI Data Bus Width |
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Data Lanes |
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Data Types |
|
Clock |
|
Simulation Test Suite
Extensive testsuite, coverage model, and verification plan with clear linkage to the specification for simple and fast compliance testing.
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Cadence Online Support
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