Overview
Best in class MIPI® SLIMbus Verification IP for your IP, SoC, and system-level design testing.
Cadence provides a mature and comprehensive Verification IP (VIP) for the SLIMbus protocol, which is part of the MIPI family. Incorporating the latest protocol updates, the SLIMbus VIP provides a complete bus functional model (BFM), integrated automatic protocol checks, coverage model, and compliance tests. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, Cadence SLIMbus VIP helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported Specifications: MIPI SLIMbus Specification version 1.3 and version 2.0.
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
---|---|
Segment distribution |
|
Multichannel stream |
|
Multiline operation |
|
Transmits and receives all message types |
|
Transport protocols |
|
Simulation Test Suite
VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.
Please contact us for further information.
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