Overview

Gold Standard for JEDEC® GDDR7 Memory Device for your IP, SoC, and System-Level Design Verification.

First-to-Market with Multiple Early Adopters of Production Designs.

This Cadence Verification IP (VIP) provides support for the JEDEC® Graphics Double Data Rate (GDDR7) SGRAM GDDR7 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for GDDR7 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

GDDR7 diagram

Product Highlights

  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Hundreds of predefined configurations based on specific memory vendors' part numbers, datasheets, or generic JEDEC definitions are available on ememory.cadence.com
  • Supports testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC
  • Transaction and memory callbacks for all protocols, model states, and device memory events
  • Ability to optionally skip initializations, trainings, or dynamically change configuration parameters
  • Packet tracker and Waveform debugger for easy debugging
  • Extensive functional coverage in SystemVerilog
  • Integrated with the DFI GDDR7 solution for IP level verification
  • Supports PAM3 signaling by Strength Modelling, Real Number Modeling (RNM)
  • Supports Linear Feedback Shift Register (LFSR) mode for a better and faster way of data trainings
  • Supports Command Address Parity with Command Blocking (CAPARBLK)

Key Features

The key features of the GDDR7 device standard supported by the Cadence GDDR7 VIP are listed below:

Feature Name

Description

Speed
  • Supports up to 32Gbps with current vendor datasheets

Device Density
  • Supports a wide range of device densities from 16Gb to 64Gb with four independent channels

Data signaling
  • High-speed using PAM3 and low-speed option for NRZ

PAM3 signaling
  • Supported using either of these three, additional pins, same pin with strengths (Strength Modelling), additional pin with real number value, like voltage (Real Number Modelling)

Supported Commands
  • Write: Write, Write Auto-Precharge
  • Read: Read, Read Auto-Precharge
  • Mode Register Set, Activate
  • Precharge: PREab, PREpb
  • Power Down Entry (PDE), Power Down Exit (PDX)
  • Self-Refresh Entry (SRE), Self-Refresh Exit (SRX)
  • Sleep Entry, Self-Refresh Sleep Entry
  • Refresh: REFab, REFpb, REFp2b
  • Refresh Management: RFMab, RFMpb
  • Training Commands

Read/Write
  • Supports configurable Read/ Write latencies
  • Supports configurable preambles, postambles and timings

Refresh
  • Supports Refresh and Refresh Management

Sleep
  • Supports Self Refresh, Sleep, Self Refresh Sleep, and Hibernate Self Refresh Sleep modes

Initialization
  • Supports power-up initialization and stable power initialization with the option to skip it

CABI and CAPAR
  • Supports command address bus inversion and command address parity functionalities

Data Training
  • Supports read and write trainings with both modes, FIFO and LFSR
Command Address Bus Training
  • Supports this training and all the possible ways to enter it
CRC
  • Supports Cyclic Redundancy Check (CRC) on write and read data
ECC Engine Test Mode
  • Supports ECC engine test mode of operation

Master Your Tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles

Learn More
Related Products
System VIP
Design IP
Xcelium Logic Simulation
Palladium Emulation