Cadence QRC RF Transistor and Substrate-level Extraction Training
日期 | 版本 | 國家/地區 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Course Description
In this course, you explore schematic simulation, layout extraction, substrate extraction , resimulation, and comparison. In this Cadence® QRC RF course, you extract a layout substrate and simulate the extracted substrate and display the noise distribution. The results are displayed by a color map overlay on the extracted layout.
Learning Objectives
After completing this course, you will be able to:
- Apply QRC extraction in the design flow
- Set up the choices for the environment
- Use the licensing system
- Run an LVS and subsequent extraction
- Compare the PVS QRC and Calibre LVS QRC flows
- Set up single and multiple corner extraction runs
- Create extracted views including substrate extracted views
- Use the QRC graphical user interface to set up and run extraction
- Run parasitic inductance extraction
- Run parasitic substrate extraction
- Select options and run the field solver for selected nets
- Run the ADE netlist and simulator to compare schematic and extracted netlists and substrate extractions.
Software Used in This Course
- Virtuoso® Schematic Editor , Analog Design Environment, Physical Verification System
Software Release(s)
- IC 6.1.5.500.12 PVE 11.1
Course Agenda
Note that this course can be tailored to better meet your needs – contact the Cadence training staff for specifics.
Sequence
- Overview of QRC Extraction
- QRC Technology Setup
- QRC Parasitic Extraction
- Extracted View Flows
- Appendix: CCL example
Audience
- Anyone interested in extracting physical layout design and substrate for resimulation comparison.
Prerequisites
You must be familiar with circuit extraction and resimulation.
Related Courses
Virtuoso Schematic Editor Virtuoso Layout Design Basics Physical Verification SystemClick here to view course learning maps, and here for complete course catalogs.
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