Low-Power Verification with Encounter Conformal Training
日期 | 版本 | 國家/地區 | 位置 | |
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Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Length: 1 day
Course Description
Learning Objectives
After completing this course, you will be able to:
- Identify features of Conformal Low-Power software
- Identify the flows for low-power verification
- Identify power intent support in Conformal Low-Power software
- Apply low-power checks on gate netlists with corresponding power intent
- Apply low-power checks on physical netlists with corresponding power intent
- Run low-power equivalency checks in different stages along with the supplied power intent
Software Used in This Course
- Conformal Low Power XL
Software Release(s)
CONFRML181
Modules in this Course
- Overview
- Preparation and Setup
- Power Intent Support (CPF and IEEE 1801)
- Synthesis Verification
- Physical Verification
- Using Conformal Low-Power Effectively
Audience
- ASIC Designers
- Design Engineers
- Digital IC Designers
- FPGA Designers
- Hardware Engineers
- Logic Designers
Prerequisites
You must have experience with or knowledge of the following:
- Have a basic understanding of Verilog language and constructs
- Have a basic understanding of one of the three CPF, UPF, or IEEE 1801 power intent formats
- Completed Logic Equivalence Checking with Conformal course or
- Have equivalent experience with the Conformal Equivalence Checker tool
Or you must have completed the following courses:
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ONLINE TRAINING
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