Overview
Best-in-Class PCI Express® Verification IP for your IP, SoC, and System-Level Design Testing
Used by all leading PCIe, IP, and SoC design verification teams for all generations.
The Cadence Verification IP (VIP) for PCI Express® (PCIe®) provides a complete bus functional model (BFM) with thousands of integrated automatic protocol checks for all three protocol layers (TL, DLL, PL) in addition to specific PIPE and PIE. Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.
Product Highlights
Key Features
The following table lists the Important features offered in the Cadence VIP for PCIe:
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Simulation Test Suite
Extensive testsuite, coverage model, and verification plan with clear linkage to the specification for simple and fast compliance testing.
Master Your Tools
Tutorials, Documentation, and Local Experts
Cadence Online Support
Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles