Overview
Gold standard for CoaXPress device for your IP, SoC, and system-level design verification.
In production since 2018.
This Cadence® Verification IP (VIP) supports the CoaXPress standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for CoaXPress is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
Supported specification: The VIP for CoaXPress supports the specification versions: 1.0, 1.1, and 1.1.1.
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
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Configurations |
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Bit Rates |
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Encode |
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Device Discovery |
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Simulation Test Suite
VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.
Please contact us for further information.
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Cadence Online Support
Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles