Webinar

CadenceTECHTALK: Addressing Large-Scale Design Challenges with Fast, Accurate STA Methodology

Solve your large-scale design challenges with the industry’s fastest STA solution that delivers superior runtime efficiency.

Join our on-demand webinar to learn how the latest innovations in the Cadence Tempus Timing Solution deliver faster design closure with excellent PPA (performance, power, and area).

In this webinar, Socionext discusses their experience using the Tempus Timing Solution to expedite STA/timing processes, enabling more ECO iterations, and enhancing their tapeout schedules. Additionally, Socionext adopted the Cadence Certus Closure Solution, Tempus DSTA, SmartScope, and Timing Context Analysis to shrink design sizes, boost runtime efficiency, and minimize memory consumption.

This webinar presents the following:

  • Advantages of the Tempus Timing Solution’s DSTA—the industry’s fastest STA solution that handles full-chip capacity—delivering a remarkable 90% reduction in memory usage per host
  • Benefits of the Cadence Certus Closure Solution, SmartScope, and Timing Context Analysis solutions—expediting ECO iteration phase from 7 to 3 days, dramatically improving productivity, and streamlining the closure of timing violations
  • Achieving rapid design closure with over billion+ cell designs optimized for production
Presenter Bio: Akihiro Nakamura is a Principal Engineer of the Global Development Group of the Back End Development division at Socionext Inc. He has 20 years of experience in physical design timing closure, including chip-level STA and timing closure methodologies to improve design productivity, especially for advanced technology nodes.

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