Model Generation and Analysis using PowerSI and Broadband SPICE Training
날짜 | 버전 | 국가 | 위치 | |
---|---|---|---|---|
04 Nov 2024 | 2023.1-HF2 | Korea, Republic Of | Gyeonggi-do-Korea Korea, Republic Of |
EnrollINQUIRE |
Scheduled upon demandOn demand | EnrollINQUIRE |
Length: 3 Days (24 hours)
Become Cadence Certified
Course Description
This course first presents model generation and analysis of a simple PCB using PowerSI. Building a simple pre-layout PCB in PowerSI followed by studying electrical parameters of signal traces reported in the Trace Properties window and comparing those electrical parameters with the electrical parameters computed using the closed form expressions are discussed in this module. Next, the process of generating S-parameters for power and signal nets of the simple pre-layout PCB, computing impedances, and loop inductances of power and signal nets are discussed in this module.
Next, this course presents model generation and analysis of a parallel bus and then a serial link system using PowerSI and Broadband SPICE tools. The methodology of generating S-parameters, first for the power-aware parallel bus interface and, next, the serial link interface of a post-layout real-world PCB is discussed in detail in this module. The process of analyzing S-parameters for the parallel bus and serial link interfaces in terms of return loss, insertion loss, open-circuit, and short-circuit impedance parameters is discussed in this module. Also, the process of generating a SPICE equivalent circuit model for the power-aware parallel bus interface of the PCB, using the Broadband SPICE tool, is illustrated in this module.
Finally, this course presents model generation and analysis of an IC package, using PowerSI and Broadband SPICE tools. The methodology of generating S-parameters for signal and power nets of a power-aware parallel bus interface and core-power delivery network of a flip-chip IC package is discussed in this module. The process of generating RLGC parameters from the PowerSI-generated S-parameters is discussed in this module. Finally, the process of generating a SPICE equivalent circuit model for the power-aware parallel bus interface and the core-power delivery network of the flip-chip IC package, using the Broadband SPICE tool, is illustrated in this module.
Learning Objectives
After completing this course, you will be able to:
- Use PowerSI and Broadband SPICE tools to generate electrical models (S-parameters and broadband SPICE equivalent circuit) of pre- and post-routed high-speed interfaces on PCBs and IC packages and perform detailed frequency-domain analysis for evaluating power and signal integrity performance of these interfaces.
Software Used in This Course
- Sigrity PowerSI 2023.1
- Sigrity Broadband SPICE 2023.1
Software Release(s)
SIGRITY2023.1-HF2
Modules in this Course
- Model Generation and Analysis of a Simple PCB Using PowerSI
- Model Generation and Analysis of Parallel Bus and Serial-Link Systems of a PCB Using PowerSI and Broadband SPICE
- Model Generation and Analysis of an IC Package Using PowerSI and Broadband SPICE
Audience
- Engineers involved in electrical model generation and frequency-domain power and signal integrity perfromance evaluation based on the development of high-speed PCB and IC package systems.
Prerequisites
You must have experience with or knowledge of the following:
- PCBs, IC packages, transmission lines, S-parameters, SPICE equivalent circuit models, and
- Practical understanding of power and signal integrity issues in high-speed interfaces of PCBs and IC packages
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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