Webinar
CadenceTECHTALK: Advanced Aging Robustness
Learn how teams can expedite their design implementation, optimization, and closure using the advanced aging analysis technology within the Tempus Timing Solution and Cadence Innovus Implementation System.
Cadence solutions offer sophisticated modeling accuracy to combat device degradation and recovery caused by variations in supply voltage, temperature, and logic conditions across the chip. This approach supports non-uniform aging stress conditions in time and across instances without the need to re-characterize cell libraries for each new stress condition. Validated to be accurate within +/-2% of SPICE, the solution delivers a substantial PPA advantage compared to other timing derate based approaches in the industry.
This webinar presents the following:
- Importance of advanced aging-aware design and analysis
- Overview of Cadence advanced aging technology
- Achievement of SPICE accuracy in aging-aware static timing analysis
- Improved PPA due to accurate aging-aware analysis
Presenter Bio
Chirayu Amin is a Sr. Software Architect in the Cadence Digital Signoff Group and works on advanced modeling for timing analysis and cell library characterization. Chirayu has 20 years of industry experience in EDA for digital and analog circuit analysis. He started his career at Intel Corporation in the Strategic CAD Lab after receiving his PhD in ECE from Northwestern University. At Cadence, Chirayu’s most recent contributions are in modeling and analysis for important physical effects impacting the timing of digital chips.