Based on the well-established NanoRoute™ engine, next-generation slack and power-driven routing with track-aware timing optimization addresses signal integrity early on and improves post-route correlation. The Innovus system includes full-flow multi-objective technology, which makes concurrent electrical and physical optimization possible. It also shares a customizable flow via a common UI and user commands with synthesis and signoff tools. As a result, you can take advantage of robust reporting and visualization, improving your design efficiency and productivity across the whole digital flow.
With block sizes growing in both cell count and complexity, the number of macros that need to be positioned in the floorplan is exploding. The Innovus system offers mixed-macro and standard-cell placement, which enables macro locations to be automatically generated, reducing the time to create an optimal floorplan from days to hours.
The latest advances in machine learning computer science are very relevant for digital implementation flows. The Innovus system incorporates machine learning technology to deliver the best PPA for the most challenging, high-performance blocks. The designer has complete control over the machine learning training, to ensure it is customized for their specific design requirements.
Cadence’s Genus™ Synthesis Solution is tightly integrated with the Innovus system, which enables a seamless move from RTL synthesis to implementation. With shared placement and optimization technology from the GigaPlace™ and GigaOpt™ engines for Genus physical synthesis, this offers a big benefit for advanced-node design convergence.
As voltage decreases in the latest FinFET process nodes, IR and EM constraints become increasingly important. The Innovus system includes comprehensive power integrity-aware placement, optimization, clock tree, and routing features to ensure IR and EM violations are addressed during implementation without impacting final PPA.
Cadence’s Tempus™ Timing Signoff Solution, Quantus™ Extraction Solution, and Voltus™ IC Power Integrity Solution are integrated with the Innovus system. With this integration, you can accurately model parasitics, timing, signal, and power integrity effects at the early stage of physical implementation, and achieve faster convergence on these electrical metrics, resulting in more efficient design closure.