Assura DRC/LVS Rules Writer Training
日期 | 版本 | 國家/地區 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Length : 2 days
Course Description
The Assura™ DRC/LVS Rules Writer course provides complete application instruction for all aspects of verification. The techniques covered are applicable to all technologies and process types:
- CMOS
- Bipolar
- High/low voltage
- Memory
- Analog/mixed signal
- ASIC
Learning Objectives
In this course you will:- Learn how to write rules for Assura physical verification
- Learn how to optimize your rules
Software
Virtuoso® Layout Editor v5.1.41Assura™ Physical Verification v3.1.4
Course Agenda
Day 1
- Introduction
- Using Assura Verification lecture and labs
- Assura Execution and Technology Setup lecture and labs
- Layer Processing lecture
- Layer Processing labs
- Defining Connectivity
- DRC Procedures lecture and labs
Day 2
- DRC Procedures labs (cont.)
- Processing Text
- Designed Device Extraction lecture and labs
- Designed Device Extraction labs (cont.)
- LVS Netlisting
- LVS Comparison lecture and labs
Audience
- CAD Engineers
- Design Kit Specialists
- Layout Designers with CAD background
Special Notes
Optimization and performance techniques are embedded in each respective application section.
Prerequisites
The student must have experience with the execution and error resolution of some type of verification tool.
Although not required, exposure to the items listed below will provide the student with a better learning experience.
- Semiconductor process background
- Physical design experience
- SKILL programming experience
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