Analog Modeling with Verilog-A Training
日期 | 版本 | 國家/地區 | 位置 | |
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Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Course Description
In this course, you use the Virtuoso® Analog Design Environment and Virtuoso Spectre® Circuit Simulator to simulate analog circuits with Verilog-A models. Verilog-A is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. You use the Verilog-A syntax, structure Verilog-A modules, and generate symbols for your Verilog-A cells for use in a system hierarchy. You also learn to format output data and to use waveform filters to improve simulation performance. In this course, you also examine the AHDL Linter feature to detect potential bugs in the Verilog-A codes.
Learning Objectives
After completing this course, you will be able to:
- Determine the importance of top-down design methodology for accelerating complex system development
- Write behavioral models of electrical circuits using the correct Verilog-A language and syntax
- Create, edit, and simulate a variety of analog models written in the Verilog-A language using the Virtuoso Analog Design Environment and the command line
- Verify that Verilog-A modules properly describe the intended function
- Use software design tools to facilitate model development
Software Used in This Course
- Virtuoso Analog Design Environment L
- Virtuoso Spectre Circuit Simulator
- Virtuoso Visualization and Analysis XL
Software Release(s)
- IC 6.1.6, MMSIM 13.1
Modules in this Course
- About This Course and Getting Help
- Basic Modeling Concepts
- Verilog-A Flow and Simulation
- The Design of Verilog-A Modules
- Verilog-A Modeling Descriptions
- Analog Event Detection
- Analog Operators and Filters
- Verilog-A Functions and Operators
- Looping and Conditional Constructs
- User-Defined and System Functions
- Displaying and Printing Results
- AHDL Linter Checks
Audience
- Analog/Mixed-Signal Designers
- IC Designers
- Library Developers
- System-level IC Designers
Prerequisites
You must have experience with or already have knowledge of the following:
- Some programming, UNIX or Linux, a text editor
You must have completed the following courses:
You must have experience with the following software:
- Virtuoso Analog Design Environment L
- Virtuoso Spectre Circuit Simulator
- Virtuoso Visualization and Analysis XL
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus
The possibilities of Verilog-A are really impressive, and I was not aware of them, even using spectre for several years.”
Michael Langenbuch, Intel
“I was very impressed by the professional attitude of the lector and satisfied with the course information I received."
Jiri Lehocky, ONSemiconductor
"Very, very good. I like the compact way the topics are presented."
Michael Asam, Infineon Technologies
"The course was very beneficial for me. I like the teacher presenting very clearly."
Pavel Londak, ONSemiconductor
"The course was at my level. I liked that it was practical with exercises to test out what we learned."
Derek Bernardon, Infineon Technologies