Overview

Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing

The Cadence Verification IP (VIP) for Universal Chiplet Interconnect Express (UCIe) is designed for easy integration in test benches at the IP, system-on-chip (SoC), and system level. The VIP for UCIe runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce the time spent on environment development and redirect it to cover a larger verification space, accelerate verification closure, and ensure end-product quality.

UCIe Diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM
  • UVM building blocks
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker and Waveform debugger for efficient debugging
  • SystemVerilog coverage model
  • Trace for issue replay

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Protocol Layer Features
  • Streaming mode
  • PCIe mode
  • Protocol FDI LSMs
  • Pseudo Protocol port - API interface to inject user-defined FLITs in the protocol layer

D2D Adapter Layer Features
  • Link Initialization
  • Adapter Initialization
  • Parameter Exchange With Remote Link Partner
  • FDI Bring Up
  • Raw (Format 1 Streaming)
  • 68B FLIT (Format 2 Streaming)
  • Standard 256B End Header FLIT (Format 3 in Streaming and PCIe)
  • Standard 256B Start Header FLIT (Format 4 in Streaming)
  • Latency Optimized 256B FLIT without optional byte (Format 5 in Streaming)
  • Latency Optimized 256B FLIT with optional byte (Format 6 in Streaming)
  • Decision Table for flit format and protocol
  • D2D Adapter FDI LSMs
  • D2D Adapter RDI SSM
  • Retry in Streaming (Format 3, 4, 5, 6)
  • Pseudo FDI port - API interface to inject user-defined Sideband and Mainband packets (FLITs) in D2D Adapter layer, bypassing FDI

PHY Features*
  • Package - Standard (16 lanes) and Advanced (64 lanes)
  • Sideband transmission
  • Mainband transmission at link speed per lane 4, 8, 12, 16, 24, 32GT/s
  • Sideband Data/clock resolution
  • Lane reversal
  • Data lane repair - single and two lane
  • Single and two lane repair with reversal
  • Clock and track lane remapping and repair
  • Valid lane remapping and repair
  • Scrambling and training pattern generation
  • Link initialization and training
  • Transmitter initiated Data to Clock point training
  • Transmitter initiated Data to Clock eye width sweep
  • Receiver initiated Data to Clock point training
  • Adapter and Remote PHY initiated PHY Retrain
  • LTSM
  • PHY RDI SSM
  • UCIe link Dynamic clock gating
  • Free running clock
  • Standard package Single Module
  • Advanced package Single Module
  • Advanced package Multi-Module link and initialization
  • Standard package Multi-Module
  • Single Module width degrade
  • Psuedo RDI port - API interface to inject user-defined Sideband and Mainband packets in PHY layer (bypassing RDI)
  • Recalibration
  • Redundant lane training

Interfaces
  • FDI (FLIT data interface connecting Protocol layer with D2D Adapter layer)
  • RDI (Raw data interface connecting D2D Adapter layer with PHY layer)
  • UCIe PHY Mainband and Sideband
  • FDI/RDI Mb Data Width 128, 256, 512, 1024, 2048, 4096, 8192 bits
  • Multi-byte width up to 4 Bytes per lane at Link/RDI/FDI
  • FDI/RDI Sb Data Width 8, 16, 32 bits
  • RDI State Machine
  • RDI Bring up flow
  • FDI State Machine
  • FDI Bring up flow
  • Rules and description for lp_wake_req/pl_wake_ack handshake
  • Rules and description for pl_clk_req/lp_clk_ack handshake
  • Rx_active_req/Sts Handshake
  • Common rules for FDI and RDI
  • Byte Mapping for FDI and RDI
  • State Request and Status
  • Reset State
  • Active State
  • LinkReset State
  • Disable State
  • Linkerror State

Sideband Features
  • Packet Types
  • Register Access Packets
  • Messages without Data
  • Messages with data payloads
  • Flow Control and Data Integrity over UCIe sideband Link between dies

Model Capabilities
  • Standalone layer, Partial stack, Full-stack
  • LTSM training bypass
  • Scrambler bypass
  • Configurable number of D2C training attempts and pattern count
  • Debug ports
  • Packet IDs for packet tracking within a layer
  • RDI SHIM
  • Model registers

Monitor Mode
  • PHY Link Monitor: Monitors UCIe PHY link excluding RDI SSM and RDI interface
  • PHY 4Path Monitor: Monitors complete PHY layer including UCIe link and RDI SSM and interface
  • PHY RDI Monitor: Monitors PHY RDI interface only and performs pin/interface rules-related checks (excluding PHY RDI SSM monitoring)
  • D2D RDI Monitor: Monitors D2D RDI interface only and performs pin/interface rules-related checks (excluding D2D RDI SSM monitoring)

Package
  • Standard (16 lanes)
  • Advanced (64 lanes)

Error Injections
  • Modifiable transaction fields through Callbacks
  • Sending to LinkError/Disabled/LinkReset in Streaming mode
  • Sending to LinkReset/Disabled in PCIe mode

Simulation Test Suite

UCIe VIP has a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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